BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
☆38Mar 15, 2026Updated 2 weeks ago
Alternatives and similar repositories for bsg_replicant
Users that are interested in bsg_replicant are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Jun 16, 2025Updated 9 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆285Feb 20, 2026Updated last month
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆654Jan 19, 2026Updated 2 months ago
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- Virtual Platform for AWS FPGA support☆16Oct 19, 2018Updated 7 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Apr 13, 2023Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Jan 13, 2023Updated 3 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 9 months ago
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated last month
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Learn and build GPU RTL from scratch☆20Aug 1, 2025Updated 7 months ago
- Jumpstart your custom DNN accelerator today. This project holds scripts to build and start containers that can compile binaries to the ze…☆10Jun 17, 2020Updated 5 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Mar 1, 2021Updated 5 years ago
- ☆16May 10, 2019Updated 6 years ago
- Morphle Logic V1.0, an open hardware asynchronous runtime reconfigurable array ARRA or PPL,FPGA,CPLD☆23Feb 12, 2023Updated 3 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Fast Symbolic Repair of Hardware Design Code☆34Jan 20, 2025Updated last year
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- "High density" digital standard cells for SKY130 provided by SkyWater.☆23Feb 22, 2023Updated 3 years ago
- A Linux-capable RISC-V multicore for and by the world☆787Updated this week
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆50Aug 24, 2024Updated last year
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- Everything needed for ulx3s FPGA☆15Oct 12, 2020Updated 5 years ago
- ☆15Oct 24, 2019Updated 6 years ago
- PyTorch compilation tutorial covering TorchScript, torch.fx, and Slapo☆17Mar 13, 2023Updated 3 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Apr 17, 2016Updated 9 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A tool for synthesizing Verilog programs☆112Aug 25, 2025Updated 7 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated last month
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆108Jan 29, 2022Updated 4 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- RTLMeter benchmark suite☆29Mar 15, 2026Updated 2 weeks ago