bespoke-silicon-group / bsg_replicant
BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
☆32Updated last week
Alternatives and similar repositories for bsg_replicant:
Users that are interested in bsg_replicant are comparing it to the libraries listed below
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- Simple runtime for Pulp platforms☆45Updated last month
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆48Updated 8 months ago
- ☆43Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- DASS HLS Compiler☆29Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 6 months ago
- ☆15Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 11 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆106Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Generic Register Interface (contains various adapters)☆113Updated 7 months ago