bespoke-silicon-group / bsg_replicant
BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
☆27Updated this week
Related projects ⓘ
Alternatives and complementary repositories for bsg_replicant
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆56Updated 2 weeks ago
- A SystemVerilog source file pickler.☆52Updated last month
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆36Updated last month
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆33Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆33Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 9 years ago
- ☆39Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated 9 months ago
- A Rocket-based RISC-V superscalar in-order core☆28Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- The multi-core cluster of a PULP system.☆56Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- The specification for the FIRRTL language☆46Updated this week
- ☆30Updated last year
- ☆52Updated 2 years ago
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- ☆15Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆48Updated 4 years ago
- Benchmarks for Yosys development☆22Updated 4 years ago