pulp-platform / banshee
☆19Updated 2 months ago
Alternatives and similar repositories for banshee:
Users that are interested in banshee are comparing it to the libraries listed below
- For contributions of Chisel IP to the chisel community.☆60Updated 4 months ago
- ☆53Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆71Updated this week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆69Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- Chisel RISC-V Vector 1.0 Implementation☆89Updated this week
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆102Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 10 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆38Updated last year
- Open source high performance IEEE-754 floating unit☆68Updated last year
- Wrappers for open source FPU hardware implementations.☆30Updated 11 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated 11 months ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- ☆32Updated 2 weeks ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆101Updated this week
- The OpenPiton Platform☆16Updated 7 months ago
- The multi-core cluster of a PULP system.☆89Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- 21st century electronic design automation tools, written in Rust.☆29Updated this week
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- ☆15Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- This is the fork of CVA6 intended for PULP development.☆19Updated this week