Alternatives and similar repositories for banshee

Users that are interested in banshee are comparing it to the libraries listed below

• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆30Updated last week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆63Updated 7 months ago
• pulp-platform / redmule
  ☆66Updated this week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆34Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated this week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆32Updated last year
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆29Updated 4 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆62Updated 5 months ago
• chipsalliance / tilelink
  ☆30Updated 6 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated 2 weeks ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated this week
• chipsalliance / espresso
  ☆40Updated 3 weeks ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆88Updated 2 weeks ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 3 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆85Updated this week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆101Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆33Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• tenstorrent / whisper
  ☆46Updated 2 weeks ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆37Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆101Updated this week
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆16Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆46Updated 8 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆47Updated this week
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆13Updated 4 months ago
• sequencer / arithmetic
  ☆33Updated 3 months ago