Alternatives and similar repositories for banshee

Users that are interested in banshee are comparing it to the libraries listed below

• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆123Updated 3 weeks ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆42Updated this week
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆161Updated this week
• pulp-platform / redmule
  ☆90Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated 3 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆135Updated last week
• chipsalliance / tilelink
  ☆38Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆98Updated 2 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated 2 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆131Updated 4 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆195Updated this week
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆44Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆56Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆52Updated this week
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• gvsoc / gvsoc
  ☆37Updated last week
• pulp-platform / fpu_ss
  CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
  ☆13Updated 2 months ago
• chipsalliance / espresso
  ☆41Updated 2 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆37Updated 2 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆38Updated 4 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆43Updated last week
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago