PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem with several modifications.
☆21Aug 25, 2026Updated 2 months ago
Alternatives and similar repositories for pulp-c910
Users that are interested in pulp-c910 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆26Mar 25, 2025Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆43Updated this week
- Differential CPU fuzzing framework from the paper "RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabiliti…☆29Sep 28, 2026Updated last month
- Dual-Core Out-of-Order MIPS CPU Design☆26May 8, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- whatever it means☆19Jun 10, 2026Updated 4 months ago
- ☆55Oct 16, 2026Updated 2 weeks ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆331Updated this week
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- ☆15Jul 12, 2020Updated 6 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆39Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Running Linux on IOb-SoC-OpenCryptoHW☆16Aug 15, 2024Updated 2 years ago
- FPGA ringoscillator for random number generation☆12Dec 22, 2025Updated 10 months ago
- FPGA Many-core Processor Implementation☆11Nov 27, 2024Updated last year
- 基于玄铁openc906，搭建最小化SoC系统☆23Apr 7, 2025Updated last year
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 9 months ago
- ☆14Dec 9, 2025Updated 10 months ago
- This is the fork of CVA6 intended for PULP development.☆26Updated this week
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆16Jan 21, 2026Updated 9 months ago
- ☆27Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- FA4-based Relative Attention Kernel developed by TML and Colfax☆18Sep 11, 2026Updated last month
- ☆16Mar 27, 2024Updated 2 years ago
- PSA-ADAC SDC-600 Secure Debug Manager library for authenticated debug☆17Mar 18, 2025Updated last year
- My blog — https://twilco.github.io☆13Apr 26, 2026Updated 6 months ago
- ☆15Updated this week
- PowerPC implemented in Verilog for an FPGA.☆14Sep 12, 2024Updated 2 years ago
- FPGA systolic array AI engine☆38Jan 2, 2026Updated 9 months ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- Sail x86 model automatically translated from the ACL2 model☆15Nov 29, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆93Apr 22, 2025Updated last year
- UM-SJTU JI VE450 2021 Summer Capstone Design Project☆10Aug 4, 2021Updated 5 years ago
- Pushing the bf16 multiplication clock frequency to the max on the nominal corner on IHP 130nm 5L node.☆16Mar 29, 2026Updated 7 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆384Updated this week
- Various FPGA projects targeting a Digilent Arty FPGA board☆11Oct 7, 2020Updated 6 years ago
- Artifact for the IEEE S&P 2025 paper: "Rapid Reversing of Non-Linear CPU Cache Slice Functions: Unlocking Physical Address Leakage"☆22Apr 3, 2026Updated 6 months ago
- ☆16Updated this week