pulp-platform / pulp-c910Links
PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem with several modifications.
☆15Updated 7 months ago
Alternatives and similar repositories for pulp-c910
Users that are interested in pulp-c910 are comparing it to the libraries listed below
Sorting:
- whatever it means☆15Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 months ago
- ☆33Updated last month
- ☆113Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆99Updated 6 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Administrative repository for the Integrated Matrix Extension Task Group☆30Updated 3 weeks ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆56Updated 5 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆19Updated 2 months ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- BlackParrot on Zynq☆47Updated 3 weeks ago
- RISC-V Nox core☆71Updated 5 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆38Updated 3 years ago
- Platform Level Interrupt Controller☆43Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Complete tutorial code.☆22Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆28Updated last month
- ☆40Updated 7 months ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆41Updated 6 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 3 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆53Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆80Updated last week
- Advanced Architecture Labs with CVA6☆72Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year