pulp-platform / hyperbus
☆21Updated 2 months ago
Alternatives and similar repositories for hyperbus:
Users that are interested in hyperbus are comparing it to the libraries listed below
- ☆24Updated last month
- Platform Level Interrupt Controller☆37Updated 10 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆23Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago
- RISCV model for Verilator/FPGA targets☆50Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- SystemVerilog FSM generator☆30Updated 10 months ago
- Ethernet MAC 10/100 Mbps☆25Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆60Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- RISC-V Nox core☆62Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated 2 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- DDR4 Simulation Project in System Verilog☆36Updated 10 years ago
- ☆59Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 weeks ago
- ☆36Updated last year
- ☆53Updated 4 years ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆33Updated 5 months ago
- Wishbone interconnect utilities☆39Updated last month
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- The multi-core cluster of a PULP system.☆89Updated 2 weeks ago
- USB Full Speed PHY☆42Updated 4 years ago
- ☆25Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆83Updated last week
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago