pulp-platform / hyperbusLinks
☆30Updated 3 weeks ago
Alternatives and similar repositories for hyperbus
Users that are interested in hyperbus are comparing it to the libraries listed below
Sorting:
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- SpinalHDL Hardware Math Library☆93Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- RISC-V Nox core☆68Updated 2 months ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Platform Level Interrupt Controller☆43Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆90Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆113Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- Verilog HDL implementation of SDRAM controller and SDRAM model☆31Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 3 months ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- ☆40Updated last year
- Generic Register Interface (contains various adapters)☆130Updated 2 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 3 months ago
- Wishbone interconnect utilities☆42Updated 8 months ago