UofT-HPRC / Tbps_CRCLinks
A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
☆15Updated last year
Alternatives and similar repositories for Tbps_CRC
Users that are interested in Tbps_CRC are comparing it to the libraries listed below
Sorting:
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- A simple DDR3 memory controller☆55Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆67Updated 8 months ago
- Ethernet interface modules for Cocotb☆64Updated last year
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆20Updated 6 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆60Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- ☆21Updated 5 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆44Updated 10 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 9 months ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- Open FPGA Modules☆23Updated 7 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- ☆24Updated last year
- UART -> AXI Bridge☆61Updated 3 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆37Updated 8 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆43Updated 4 months ago
- ☆10Updated last year
- UART models for cocotb☆29Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated last year
- ☆58Updated 4 years ago