A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
☆20Oct 23, 2023Updated 3 years ago
Alternatives and similar repositories for Tbps_CRC
Users that are interested in Tbps_CRC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ethernet switch implementation written in Verilog☆66Jun 13, 2023Updated 3 years ago
- Reverse engineering of the CATC USB Chief driver☆15Dec 26, 2025Updated 10 months ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 3 years ago
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆33Feb 22, 2024Updated 2 years ago
- Test dashboard for verification features in Verilator☆35Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Open source FPGA-based NIC and platform for in-network compute☆18May 22, 2024Updated 2 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆52Apr 22, 2024Updated 2 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated 2 years ago
- Low level arithmetic primitives in RTL☆25Apr 3, 2020Updated 6 years ago
- ☆23Sep 18, 2026Updated last month
- SPIREG - SPI slave logic for register access☆11Nov 12, 2025Updated 11 months ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 4 months ago
- NanoRV32 -- A small RV32I[MC] core capable of running RTOS☆14Nov 18, 2022Updated 3 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆132Mar 6, 2026Updated 7 months ago
- Ethernet interface modules for Cocotb☆83Aug 28, 2026Updated 2 months ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 3 years ago
- A high-throughput, parameterized, parallel crc hardware implementation.☆12Jun 2, 2024Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆122Oct 16, 2026Updated 2 weeks ago
- ☆16Aug 13, 2022Updated 4 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Jan 19, 2026Updated 9 months ago
- AXI interface modules for Cocotb☆368Aug 24, 2026Updated 2 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- video stream scaler based on FPGA and verilog☆20Mar 28, 2024Updated 2 years ago
- ☆13May 15, 2015Updated 11 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆1,002Aug 28, 2026Updated 2 months ago
- Clock Data Recovery | 時鐘數據恢復☆12Aug 9, 2020Updated 6 years ago
- ORPSoC fork (from git://openrisc.net/stefan/orpsoc) for de0_nano board with custom made expansion board☆12Sep 26, 2013Updated 13 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆254Oct 26, 2026Updated last week
- ☆10May 27, 2026Updated 5 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- cryptography ip-cores in vhdl / verilog☆43Feb 20, 2021Updated 5 years ago
- Senior Design Project at UW-Madison ECE☆17May 4, 2023Updated 3 years ago
- 🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation☆13Apr 30, 2026Updated 6 months ago
- 从上位机采用UART或以太网将位流文件烧写到片外Flash中，利用Xilinx FPGA的Multiboot特性，进行OTA(over the air)在线升级。如升级失败，可以回到原来的位流文件。☆13Dec 7, 2023Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆42Oct 16, 2026Updated 2 weeks ago
- GateMate's PHY Interface for PCI Express (PIPE)☆15Oct 21, 2026Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆125Nov 26, 2025Updated 11 months ago