pulp-platform / crocLinks
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
☆201Updated this week
Alternatives and similar repositories for croc
Users that are interested in croc are comparing it to the libraries listed below
Sorting:
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Fabric generator and CAD tools.☆215Updated last week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 2 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 4 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆74Updated 3 years ago
- ASIC implementation flow infrastructure, successor to OpenLane☆276Updated this week
- Physical Design Flow from RTL to GDS using Opensource tools.☆120Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- A Fast, Low-Overhead On-chip Network☆265Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated this week
- A demo system for Ibex including debug support and some peripherals☆84Updated 2 weeks ago
- Curriculum for a university course to teach chip design using open source EDA tools☆133Updated 2 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆238Updated last week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- ☆113Updated 2 months ago
- RISC-V Nox core☆71Updated 6 months ago
- SystemVerilog frontend for Yosys☆194Updated last week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Updated 5 years ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆103Updated last year
- A complete open-source design-for-testing (DFT) Solution☆179Updated 5 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- Control and status register code generator toolchain☆172Updated 2 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆74Updated 4 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆104Updated 8 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- SystemVerilog synthesis tool☆226Updated 10 months ago