pulp-platform / crocLinks
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
☆120Updated this week
Alternatives and similar repositories for croc
Users that are interested in croc are comparing it to the libraries listed below
Sorting:
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- A demo system for Ibex including debug support and some peripherals☆73Updated last month
- Curriculum for a university course to teach chip design using open source EDA tools☆94Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆214Updated last week
- Introductory course into static timing analysis (STA).☆94Updated last week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆151Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- RISC-V Nox core☆65Updated 3 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆64Updated 2 years ago
- ☆96Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- SystemVerilog frontend for Yosys☆135Updated last week
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆95Updated 2 weeks ago
- Basic RISC-V Test SoC☆137Updated 6 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆201Updated 2 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆168Updated 7 months ago
- Fabric generator and CAD tools.☆190Updated this week
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆60Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- An overview of TL-Verilog resources and projects☆81Updated 3 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated last week
- RISC-V Verification Interface☆97Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago