This is the fork of CVA6 intended for PULP development.
☆22Mar 14, 2026Updated last week
Alternatives and similar repositories for cva6
Users that are interested in cva6 are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Mar 11, 2026Updated last week
- Administrative repository for the Integrated Matrix Extension Task Group☆34Dec 15, 2025Updated 3 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆323Updated this week
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆40Feb 23, 2026Updated 3 weeks ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Interactive Theorem Proving course using HOL4☆13Jun 21, 2023Updated 2 years ago
- RISC-V Integrated Matrix Development Repository☆21Updated this week
- ☆10Nov 12, 2019Updated 6 years ago
- 💾 FreeRTOS port for the NEORV32 RISC-V Processor.☆13Updated this week
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated 2 years ago
- OpenMZ, a security kernel for RISC-V targeting secure coprocessors and secure embedded systems.☆14Jun 26, 2020Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- A simple, scalable, source-synchronous, all-digital DDR link☆36Updated this week
- Convert a Image to a COE file for Vivado☆10Apr 14, 2025Updated 11 months ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- ☆13Aug 14, 2023Updated 2 years ago
- Tutorial☆15Jun 13, 2020Updated 5 years ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆14Dec 22, 2025Updated 3 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆500Mar 14, 2026Updated last week
- Branch Predictor Optimization for BlackParrot☆15Mar 24, 2024Updated last year
- ☆12May 27, 2024Updated last year
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- ☆10Jan 30, 2017Updated 9 years ago
- MultiZone free and open API definition☆15Oct 26, 2021Updated 4 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- a port of suckless terminal (st) to rust☆22Aug 6, 2025Updated 7 months ago
- ☆32Jan 21, 2026Updated 2 months ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Graphics SIG organizational information☆40Jan 10, 2024Updated 2 years ago
- A configurable SRAM generator☆58Mar 4, 2026Updated 2 weeks ago
- Mirror of git://qemu.org/capstone.git☆10Mar 2, 2026Updated 2 weeks ago
- Verilog hardware abstraction library☆49Mar 13, 2026Updated last week
- Repo for PyChart 1.39, refs http://download.gna.org/pychart/☆10Sep 29, 2014Updated 11 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆33Apr 13, 2021Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 2 months ago
- RISC-V Verification Interface☆145Mar 6, 2026Updated 2 weeks ago
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated last year
- AXI X-Bar☆19Apr 8, 2020Updated 5 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago