This is the fork of CVA6 intended for PULP development.
☆25Sep 19, 2026Updated this week
Alternatives and similar repositories for cva6
Users that are interested in cva6 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Jul 16, 2026Updated 2 months ago
- Administrative repository for the Integrated Matrix Extension Task Group☆39Jul 27, 2026Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆367Updated this week
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- RISC-V Integrated Matrix Development Repository☆26Aug 24, 2026Updated 3 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆10Nov 12, 2019Updated 6 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated 2 years ago
- OpenMZ, a security kernel for RISC-V targeting secure coprocessors and secure embedded systems.☆14Jun 26, 2020Updated 6 years ago
- CORE-V MCU UVM Environment and Test Bench☆29Jul 19, 2024Updated 2 years ago
- 💾 FreeRTOS port for the NEORV32 RISC-V Processor.☆16Sep 2, 2026Updated 2 weeks ago
- Branch Predictor Optimization for BlackParrot☆15Mar 24, 2024Updated 2 years ago
- Capability-based real-time separation kernel for secure embedded RISC-V.☆19Sep 1, 2026Updated 2 weeks ago
- MultiZone free and open API definition☆15Oct 26, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆548Aug 19, 2026Updated last month
- A simple, scalable, source-synchronous, all-digital DDR link☆42Sep 1, 2026Updated 2 weeks ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆49Jul 22, 2026Updated last month
- ☆14Aug 14, 2023Updated 3 years ago
- Tutorial☆16Jun 13, 2020Updated 6 years ago
- ☆10Jan 30, 2017Updated 9 years ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆15Dec 22, 2025Updated 8 months ago
- a port of suckless terminal (st) to rust☆22Aug 6, 2025Updated last year
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆35Apr 13, 2021Updated 5 years ago
- ☆37May 21, 2026Updated 3 months ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Graphics SIG organizational information☆40Jan 10, 2024Updated 2 years ago
- A modular hardware abstraction library☆53Updated this week
- Mirror of git://qemu.org/capstone.git☆10Updated this week
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code(使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 3 years ago
- Repo for PyChart 1.39, refs http://download.gna.org/pychart/☆10Sep 29, 2014Updated 11 years ago
- SystemVerilog modules and classes commonly used for verification☆58Jan 5, 2026Updated 8 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- CV32E40X Design-Verification environment☆19Jun 2, 2026Updated 3 months ago
- A demo system for Ibex including debug support and some peripherals☆99Jul 16, 2026Updated 2 months ago
- High-Speed Hardware Architecture for Falcon Signature Generation Algorithm☆15Feb 27, 2025Updated last year
- ☆16May 25, 2026Updated 3 months ago
- This repo hold information on the open-standard OVP APIs☆21Dec 11, 2025Updated 9 months ago
- This is use FPGA of Xilinx ZYNQ-7000 ZC702☆16Jul 2, 2017Updated 9 years ago