pulp-platform / cva6
This is the fork of CVA6 intended for PULP development.
☆19Updated last week
Alternatives and similar repositories for cva6:
Users that are interested in cva6 are comparing it to the libraries listed below
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆54Updated last month
- ☆92Updated last year
- Advanced Architecture Labs with CVA6☆57Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆145Updated 3 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 11 months ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- ☆43Updated 6 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆64Updated 10 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆195Updated last week
- The multi-core cluster of a PULP system.☆89Updated 2 weeks ago
- Pure digital components of a UCIe controller☆60Updated 2 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆74Updated this week
- BlackParrot on Zynq☆38Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆104Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 6 months ago
- ☆54Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆51Updated 3 months ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- ☆11Updated 4 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last month
- Unit tests generator for RVV 1.0☆82Updated 3 weeks ago