Alternatives and similar repositories for cva6

Users that are interested in cva6 are comparing it to the libraries listed below

• chipsalliance / uvm-verilator
  ☆95Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 3 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆78Updated last week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 3 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• pulp-platform / fpu
  ☆50Updated 6 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated last year
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆56Updated this week
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆41Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆97Updated this week
• pulp-platform / axi_llc
  ☆30Updated last month
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆48Updated 5 months ago
• lowRISC / riscv-compliance
  TEMPORARY FORK of the riscv-compliance repository
  ☆27Updated 4 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆110Updated last week
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆34Updated 4 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 7 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆92Updated this week
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆32Updated 7 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago