pulp-platform / cva6Links
This is the fork of CVA6 intended for PULP development.
☆22Updated this week
Alternatives and similar repositories for cva6
Users that are interested in cva6 are comparing it to the libraries listed below
Sorting:
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆93Updated 3 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆124Updated last week
- ☆107Updated 2 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated this week
- Advanced Architecture Labs with CVA6☆71Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆187Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆243Updated this week
- CVA6 SDK containing RISC-V tools and Buildroot☆75Updated last month
- Unit tests generator for RVV 1.0☆95Updated 2 weeks ago
- BlackParrot on Zynq☆47Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- The multi-core cluster of a PULP system.☆109Updated 3 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- A dynamic verification library for Chisel.☆158Updated last year
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- Chisel RISC-V Vector 1.0 Implementation☆121Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆114Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- RISC-V Verification Interface☆124Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Administrative repository for the Integrated Matrix Extension Task Group☆30Updated last month
- Verilog/SystemVerilog Guide☆75Updated last year
- ☆57Updated 6 years ago
- ☆88Updated this week
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆94Updated last year
- Simple single-port AXI memory interface☆47Updated last year
- Self checking RISC-V directed tests☆115Updated 5 months ago