pulp-platform / cva6Links
This is the fork of CVA6 intended for PULP development.
☆22Updated this week
Alternatives and similar repositories for cva6
Users that are interested in cva6 are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- ☆113Updated 2 months ago
- Advanced Architecture Labs with CVA6☆76Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- Scalable Interface for RISC-V ISA Extensions☆23Updated this week
- ☆33Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆267Updated last week
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- CVA6 SDK containing RISC-V tools and Buildroot☆78Updated last week
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆19Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- ☆58Updated 6 years ago
- Simple single-port AXI memory interface☆49Updated last year
- BlackParrot on Zynq☆48Updated this week
- matrix-coprocessor for RISC-V☆30Updated last month
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- A dynamic verification library for Chisel.☆160Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- Administrative repository for the Integrated Matrix Extension Task Group☆33Updated last month
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆20Updated last month