Alternatives and similar repositories for cheshire-ihp130-o:

Users that are interested in cheshire-ihp130-o are comparing it to the libraries listed below

• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated 3 weeks ago
• pulp-platform / svase
  ☆31Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆100Updated last week
• rahulk29 / sram22
  A configurable SRAM generator
  ☆48Updated 4 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated last month
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆14Updated 2 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆86Updated this week
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆55Updated last year
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆27Updated last week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated 4 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆39Updated last week
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• idea-fasoc / fasoc
  ☆54Updated last year
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆42Updated 3 weeks ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 5 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆81Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 5 months ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago