Alternatives and similar repositories for cheshire-ihp130-o

Users that are interested in cheshire-ihp130-o are comparing it to the libraries listed below

• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated last year
• pulp-platform / svase
  ☆32Updated 4 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆42Updated last week
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆13Updated 8 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 2 months ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆14Updated last month
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆56Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 2 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆77Updated this week
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆30Updated last month
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆117Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆110Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated this week
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• openhwgroup / core-v-polara-apu
  The OpenPiton Platform
  ☆16Updated 9 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 6 months ago