pulp-platform / cheshire-ihp130-oLinks
☆58Updated 9 months ago
Alternatives and similar repositories for cheshire-ihp130-o
Users that are interested in cheshire-ihp130-o are comparing it to the libraries listed below
Sorting:
- ☆33Updated last year
- An automatic clock gating utility☆51Updated 9 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- A configurable SRAM generator☆57Updated 4 months ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆155Updated 2 weeks ago
- RISC-V Nox core☆71Updated 5 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated this week
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- An open source generator for standard cell based memories.☆14Updated 9 years ago
- Characterizer☆31Updated last month
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- ☆57Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 2 months ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- SpiceBind – spice inside HDL simulator☆56Updated 6 months ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆44Updated last month
- Open source process design kit for 28nm open process☆72Updated last year
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆21Updated last week