cornell-zhang / bnn-fpgaLinks
Binarized Convolutional Neural Networks on Software-Programmable FPGAs
☆303Updated 4 years ago
Alternatives and similar repositories for bnn-fpga
Users that are interested in bnn-fpga are comparing it to the libraries listed below
Sorting:
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 5 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆181Updated 8 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆216Updated 6 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆143Updated 7 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆226Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 7 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆272Updated 5 years ago
- A convolutional neural network implemented in hardware (verilog)☆157Updated 7 years ago
- FPGA Accelerator for CNN using Vivado HLS☆317Updated 3 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆141Updated 7 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆258Updated 2 years ago
- ☆247Updated 4 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆89Updated 6 years ago
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆181Updated last year
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆162Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆153Updated 5 years ago
- ☆84Updated 4 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆345Updated 4 months ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆154Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆184Updated 7 years ago
- Vitis HLS Library for FINN☆198Updated this week
- CNN acceleration on virtex-7 FPGA with verilog HDL☆446Updated 7 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆229Updated 4 months ago
- DPU on PYNQ☆221Updated last year
- OpenCL Labs for PAPAA Summer School 2016 Edition☆46Updated 7 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- Getting Started with Xilinx ML Suite☆339Updated 4 years ago
- PYNQ, Neural network Language model, Overlay☆107Updated 6 years ago
- ☆143Updated 6 years ago
- Quantized Neural Networks (QNNs) on PYNQ☆689Updated 3 years ago