WenqiJiang / FPGA-Based-RNN-Accelerator-Using-Vivado-HLSLinks
This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code into Hardware Description Languages (HDL).
☆23Updated 6 years ago
Alternatives and similar repositories for FPGA-Based-RNN-Accelerator-Using-Vivado-HLS
Users that are interested in FPGA-Based-RNN-Accelerator-Using-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- Some attempts to build CNN on PYNQ.☆24Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆98Updated last year
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- ☆48Updated 7 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆26Updated 3 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆31Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- 中文:☆103Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆12Updated last year
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆28Updated last year
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago