Alternatives and similar repositories for HLS-LeNet

Users that are interested in HLS-LeNet are comparing it to the libraries listed below

• canteen-man / CNN_FPGA_ZYNQ_PYNQ
  hls code zynq 7020 pynq z2 CNN
  ☆85Updated 6 years ago
• mfarhadi / CNNIOT
  ☆46Updated 7 years ago
• GeneralZDS / FPGA-DCNN-Accelerator
  基于HLS的高效深度卷积神经网络FPGA实现方法
  ☆70Updated 5 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• FloyedShen / mnist_hls
  Lenet for MNIST handwritten digit recognition using Vivado hls tool
  ☆37Updated 4 years ago
• ZhaoqxCN / PYNQ-CNN-ATTEMPT
  Some attempts to build CNN on PYNQ.
  ☆24Updated 5 years ago
• hisrg / PYNQ_CNN_Accelerator_Tutorial
  中文：
  ☆101Updated 5 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆64Updated 4 months ago
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆48Updated 7 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 3 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆48Updated 5 years ago
• Microdent / Handwritten_Mathematical_Calculator_on_FPGA
  A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.
  ☆40Updated 4 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆45Updated 4 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆51Updated 7 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 5 years ago
• zhongguanggong / ggz
  使用FPGA实现CNN模型
  ☆15Updated 5 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆103Updated 6 years ago
• ignperez-udec / MobileNet-V2-inference-HLS
  Codes to implement MobileNet V2 in a FPGA
  ☆25Updated 4 years ago
• pp-Innovate / FPGA-ZynqNet
  FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
  ☆112Updated 7 years ago
• manoharvhr / PYNQ-Torch
  PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
  ☆71Updated 4 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆22Updated 4 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆52Updated 3 years ago
• JunnanShan / AlexNet-FPGA-implementation
  This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.
  ☆21Updated 7 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆113Updated 4 years ago
• ilaydayaman / CNN_for_SLR
  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
  ☆95Updated last year
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆37Updated 4 years ago
• WenqiJiang / FPGA-Based-RNN-Accelerator-Using-Vivado-HLS
  This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …
  ☆23Updated 5 years ago