pkuzjx / EDA-wikiLinks
EDA wiki
☆135Updated last month
Alternatives and similar repositories for EDA-wiki
Users that are interested in EDA-wiki are comparing it to the libraries listed below
Sorting:
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆107Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆162Updated 7 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆88Updated 7 months ago
- An integrated CGRA design framework☆91Updated 8 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆192Updated 5 years ago
- ☆216Updated 8 months ago
- Collection of digital hardware modules & projects (benchmarks)☆74Updated this week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆103Updated 5 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆60Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆148Updated last week
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆187Updated 6 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated this week
- A dynamic verification library for Chisel.☆159Updated last year
- ☆107Updated 6 years ago
- A Chisel RTL generator for network-on-chip interconnects☆223Updated last month
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆70Updated 6 months ago
- ☆45Updated last year
- GPU-based logic synthesis tool☆97Updated 2 weeks ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆102Updated 3 years ago
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆41Updated last year
- A logic synthesis tool☆82Updated 3 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆218Updated 3 weeks ago
- high-performance RTL simulator☆184Updated last year
- ☆40Updated 3 years ago
- This is a python repo for flattening Verilog☆20Updated 6 months ago
- An open-source benchmark for generating design RTL with natural language☆150Updated last year
- An infrastructure for integrated EDA☆42Updated 2 years ago
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆187Updated 6 months ago