yzwangfeng / reram-synthesis
A synthesis flow for hybrid processing-in-RRAM modes
☆12Updated 3 years ago
Alternatives and similar repositories for reram-synthesis:
Users that are interested in reram-synthesis are comparing it to the libraries listed below
- ☆16Updated 3 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆31Updated last month
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆26Updated 10 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Benchmarks for Approximate Circuit Synthesis☆15Updated 4 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 6 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated last week
- ☆34Updated 3 years ago
- DASS HLS Compiler☆29Updated last year
- This is a python repo for flattening Verilog☆16Updated 2 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆32Updated this week
- ☆57Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆45Updated last month
- A graph linear algebra overlay☆51Updated last year
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago
- ☆23Updated 4 years ago
- ☆25Updated 10 months ago
- EQueue Dialect☆40Updated 3 years ago
- ☆15Updated 2 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated last year
- HW accelerator mapping optimization framework for in-memory computing☆22Updated 2 months ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated last month
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- ☆27Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 weeks ago
- ☆12Updated 7 months ago