yzwangfeng / reram-synthesisLinks
A synthesis flow for hybrid processing-in-RRAM modes
☆12Updated 4 years ago
Alternatives and similar repositories for reram-synthesis
Users that are interested in reram-synthesis are comparing it to the libraries listed below
Sorting:
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆30Updated 10 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆12Updated 4 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated last month
- ☆14Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- CGRA framework with vectorization support.☆32Updated this week
- ☆16Updated 3 years ago
- ☆24Updated 4 years ago
- ☆15Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 5 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆36Updated 4 years ago
- DATuner Repository☆18Updated 6 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆50Updated 3 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 9 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 5 months ago
- ☆27Updated 7 years ago
- ☆31Updated 3 months ago
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆43Updated 3 months ago
- ☆25Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆53Updated 2 months ago
- ☆60Updated 2 months ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated 2 years ago
- EQueue Dialect☆40Updated 3 years ago