Alternatives and similar repositories for ACEC_benchmarks

Users that are interested in ACEC_benchmarks are comparing it to the libraries listed below

• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆23Updated 3 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆25Updated 2 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated last week
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 8 months ago
• iscas-tis / CHA
  ☆19Updated last year
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated last month
• amahzoon / genmul
  ☆16Updated 4 years ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated last month
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆33Updated 11 months ago
• sterin / super-prove-build
  ☆13Updated 4 years ago
• gpt4rtl / AutoSVA2
  ☆16Updated last year
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• efeslab / hardware-bugbase
  ☆18Updated last year
• yuzeng2333 / autoGenILA
  Automatic generation of architecture-level models for hardware from its RTL design.
  ☆13Updated 2 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 2 months ago
• milo168 / FPGA25_SAT_Accel
  FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository
  ☆12Updated 4 months ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆57Updated this week
• mohdomama / Quine-McCluskey
  A Python/C++ implementation of Quine McCluskey(Tabulation) method.
  ☆12Updated 6 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 3 years ago
• ckchengucsd / SMTCellUCSD
  Cell Layout Generation for DTCO/STCO Exploration Toolkit
  ☆16Updated last month
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 6 years ago