Alternatives and similar repositories for ACEC_benchmarks

Users that are interested in ACEC_benchmarks are comparing it to the libraries listed below

• fangwenji / tacas23-wasim
  ☆12Updated 3 years ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 3 weeks ago
• iscas-tis / CHA
  ☆19Updated last year
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆13Updated last year
• amahzoon / genmul
  ☆19Updated 5 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆35Updated 9 months ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 6 months ago
• sterin / super-prove-build
  ☆14Updated 5 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year
• efeslab / hardware-bugbase
  ☆20Updated last year
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis
  ☆30Updated this week
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆13Updated 2 months ago
• yuzeng2333 / autoGenILA
  Automatic generation of architecture-level models for hardware from its RTL design.
  ☆14Updated 2 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated 2 years ago
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 6 years ago
• ckchengucsd / SMTCellUCSD
  Cell Layout Generation for DTCO/STCO Exploration Toolkit
  ☆21Updated 7 months ago
• gpt4rtl / AutoSVA2
  ☆17Updated 2 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆17Updated 7 years ago
• comsec-group / cellift-yosys
  A fork of Yosys that integrates the CellIFT pass
  ☆13Updated 5 months ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated 7 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆32Updated 11 months ago
• mohdomama / Quine-McCluskey
  A Python/C++ implementation of Quine McCluskey(Tabulation) method.
  ☆12Updated 7 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year