Alternatives and similar repositories for multgen

Users that are interested in multgen are comparing it to the libraries listed below

• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 4 months ago
• efeslab / hardware-bugbase
  ☆18Updated 11 months ago
• iscas-tis / CHA
  ☆19Updated 10 months ago
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• gpt4rtl / AutoSVA2
  ☆15Updated last year
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆23Updated 4 months ago
• sterin / super-prove-build
  ☆13Updated 4 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆43Updated 3 weeks ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 7 months ago
• pulp-platform / ELAU
  ☆18Updated 11 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆21Updated last month
• mflowgen / skywater-130nm
  ASIC Design kit for Skywater 130 for use with mflowgen
  ☆12Updated 2 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 8 months ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆22Updated 4 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆72Updated 4 years ago
• euphoric-hardware / rtl-simulation-reading
  ☆14Updated 2 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆52Updated this week
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• wincle626 / HLS_Legup
  ☆27Updated 7 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆34Updated 4 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year