pku-dasys / cocoonLinks
An infrastructure for integrated EDA
☆41Updated 2 years ago
Alternatives and similar repositories for cocoon
Users that are interested in cocoon are comparing it to the libraries listed below
Sorting:
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- EDA wiki☆53Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆58Updated last month
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated 2 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 3 months ago
- Dataset for ML-guided Accelerator Design☆37Updated 9 months ago
- ☆60Updated this week
- DASS HLS Compiler☆29Updated last year
- ☆28Updated 7 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- This is a python repo for flattening Verilog☆19Updated 3 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- An integrated CGRA design framework☆90Updated 5 months ago
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- A hardware synthesis framework with multi-level paradigm☆40Updated 7 months ago
- OpenDesign Flow Database☆16Updated 6 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 10 months ago
- ☆45Updated 7 months ago
- Public release☆57Updated 5 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆51Updated 2 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆16Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Next generation CGRA generator☆113Updated 3 weeks ago
- ☆15Updated 3 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- EDA wiki☆131Updated 5 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆47Updated 8 months ago