saleh1204 / sis
Logic Synthesis System from UC Berkeley (Unofficial Distribution)
☆15Updated 5 years ago
Alternatives and similar repositories for sis:
Users that are interested in sis are comparing it to the libraries listed below
- ☆15Updated 4 years ago
- This is a python repo for flattening Verilog☆15Updated last month
- ☆12Updated last year
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated last month
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆30Updated 3 weeks ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆17Updated 4 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 7 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago
- ☆14Updated 2 years ago
- Hardware Model Checker☆32Updated this week
- Research paper based on or related to ABC.☆25Updated this week
- Benchmarks for Approximate Circuit Synthesis☆15Updated 4 years ago
- ☆12Updated 2 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆23Updated 2 years ago
- Logic optimization and technology mapping tool.☆18Updated last year
- RISC-V Formal in Chisel☆10Updated 10 months ago
- Random Generator of Btor2 Files☆9Updated last year
- This is a repo to store circuit design datasets☆15Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆41Updated 5 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 5 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆13Updated 2 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- ☆25Updated 9 months ago
- A Formal Verification Framework for Chisel☆18Updated 10 months ago
- ☆27Updated 9 months ago
- ☆17Updated 7 months ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- ☆14Updated last year
- ILA Model Database☆22Updated 4 years ago