saleh1204 / sisLinks
Logic Synthesis System from UC Berkeley (Unofficial Distribution)
☆15Updated 6 years ago
Alternatives and similar repositories for sis
Users that are interested in sis are comparing it to the libraries listed below
Sorting:
- ☆18Updated 4 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 3 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Updated 6 years ago
- ☆19Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆38Updated last year
- ☆16Updated 2 years ago
- ☆10Updated 4 years ago
- Arithmetic multiplier benchmarks☆11Updated 8 years ago
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- ☆12Updated 2 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆20Updated 11 months ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Updated 2 years ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- ☆17Updated 2 years ago
- ☆20Updated 3 years ago
- A Formal Verification Framework for Chisel☆18Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 7 months ago
- Integer Multiplier Generator for Verilog☆23Updated 4 months ago
- A generic parser and tool package for the BTOR2 format.☆45Updated 2 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Updated 9 years ago
- Research paper based on or related to ABC.☆60Updated 2 weeks ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆33Updated 7 months ago
- ☆14Updated 5 years ago
- ☆13Updated 4 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Updated 3 years ago
- ILA Model Database☆24Updated 5 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆21Updated 6 months ago