OSCPU / yosys-staLinks
☆83Updated 6 months ago
Alternatives and similar repositories for yosys-sta
Users that are interested in yosys-sta are comparing it to the libraries listed below
Sorting:
- ☆87Updated 3 weeks ago
- ☆67Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆181Updated last year
- ☆70Updated 2 years ago
- ☆67Updated 8 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- Pick your favorite language to verify your chip.☆70Updated this week
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 5 months ago
- Modern co-simulation framework for RISC-V CPUs☆158Updated this week
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 6 months ago
- Documentation for XiangShan Design☆35Updated last week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆212Updated 4 months ago
- ☆30Updated 2 months ago
- 关于移植模型至gemmini的文档☆30Updated 3 years ago
- ☆104Updated last week
- ☆156Updated this week
- ☆198Updated 3 months ago
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆21Updated 7 years ago
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆15Updated last year
- Collect some IC textbooks for learning.☆167Updated 3 years ago
- A framework for ysyx flow☆12Updated 11 months ago
- Build mini linux for your own RISC-V emulator!☆23Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆143Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- 香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境☆29Updated last year
- ☆44Updated 3 years ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- ☆64Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆116Updated 7 months ago