Alternatives and similar repositories for OpenEdgeCGRA:

Users that are interested in OpenEdgeCGRA are comparing it to the libraries listed below

• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆61Updated 2 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆66Updated last week
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆20Updated 11 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆29Updated this week
• esl-epfl / HEEPsilon
  A low power platform based on X-HEEP and integrating the ESL-CGRA
  ☆13Updated 5 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 5 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆121Updated last week
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• VeriGOOD-ML / public
  ☆58Updated last year
• pnnl / soda-opt
  ☆42Updated 2 weeks ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆33Updated this week
• lana555 / dynamatic
  ☆86Updated last year
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated 2 weeks ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆50Updated last month
• hngenc / stellar
  ☆26Updated 4 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆48Updated last week
• black-parrot / black-parrot-sim
  ☆11Updated 4 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆78Updated 6 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated last year
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 2 months ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆45Updated 2 weeks ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆33Updated 2 weeks ago
• hyoukjun / OpenSMART
  Public release
  ☆50Updated 5 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆45Updated this week
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• StanfordAHA / aha
  ☆55Updated this week