esl-epfl / OpenEdgeCGRALinks
An Open-Hardware CGRA for accelerated computation on the edge.
☆41Updated 3 months ago
Alternatives and similar repositories for OpenEdgeCGRA
Users that are interested in OpenEdgeCGRA are comparing it to the libraries listed below
Sorting:
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated this week
- An Open-Source Tool for CGRA Accelerators☆82Updated 5 months ago
- An Open-Source Tool for CGRA Accelerators☆30Updated 4 months ago
- ☆62Updated last week
- ☆57Updated 7 months ago
- ☆87Updated last year
- An integrated CGRA design framework☆91Updated 10 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last month
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- CGRA framework with vectorization support.☆43Updated 2 weeks ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- ☆65Updated 9 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆167Updated 2 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- Public release☆58Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 6 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆72Updated 6 months ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 7 months ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆180Updated 5 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- ☆20Updated 8 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 3 weeks ago