esl-epfl / CompigraLinks
☆11Updated 4 months ago
Alternatives and similar repositories for Compigra
Users that are interested in Compigra are comparing it to the libraries listed below
Sorting:
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- ☆44Updated last week
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- ☆53Updated 2 months ago
- ☆86Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 8 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆72Updated 3 weeks ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆35Updated 2 weeks ago
- An Open-Source Tool for CGRA Accelerators☆21Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆122Updated 5 years ago
- CGRA Compilation Framework☆83Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- ☆15Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated 10 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- CGRA framework with vectorization support.☆30Updated 3 weeks ago
- ☆29Updated 7 months ago
- RTL implementation of Flex-DPE.☆100Updated 5 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆59Updated last week
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- EQueue Dialect☆40Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆129Updated last week
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆91Updated last year
- A hardware synthesis framework with multi-level paradigm☆39Updated 4 months ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆36Updated 2 years ago
- An integrated CGRA design framework☆89Updated 2 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago