esl-epfl / CompigraLinks
☆14Updated 2 months ago
Alternatives and similar repositories for Compigra
Users that are interested in Compigra are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆74Updated 3 weeks ago
- ☆49Updated 3 months ago
- CGRA Compilation Framework☆88Updated 2 years ago
- ☆59Updated 6 months ago
- An Open-Source Tool for CGRA Accelerators☆24Updated 3 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 3 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆63Updated 11 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- ☆97Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- An integrated CGRA design framework☆91Updated 6 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆47Updated 2 months ago
- ☆87Updated last year
- A scalable High-Level Synthesis framework on MLIR☆278Updated last year
- ☆61Updated this week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆139Updated 3 months ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆225Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last month
- ☆58Updated 2 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆113Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆69Updated 6 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆125Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 8 months ago