Alternatives and similar repositories for Compigra:

Users that are interested in Compigra are comparing it to the libraries listed below

• pnnl / soda-opt
  ☆44Updated last month
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 6 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆64Updated last week
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆49Updated last month
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆29Updated 3 weeks ago
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆21Updated last year
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆121Updated 5 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆67Updated this week
• hngenc / stellar
  ☆26Updated 5 months ago
• lana555 / dynamatic
  ☆86Updated last year
• maestro-project / gamma
  ☆39Updated 9 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆29Updated last week
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆83Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated last month
• esl-epfl / HEEPsilon
  A low power platform based on X-HEEP and integrating the ESL-CGRA
  ☆14Updated 6 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆71Updated 5 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 3 months ago
• Xilinx / merlin-compiler
  ☆57Updated last year
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆24Updated 7 months ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆43Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆74Updated 3 years ago
• Yinxiao-Feng / chiplet-network-sim
  ☆28Updated 4 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆124Updated this week
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆34Updated 3 weeks ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆36Updated 5 months ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆64Updated 9 months ago