arcade-lab / tia-infrastructureLinks
☆19Updated 8 years ago
Alternatives and similar repositories for tia-infrastructure
Users that are interested in tia-infrastructure are comparing it to the libraries listed below
Sorting:
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆87Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 4 months ago
- Next generation CGRA generator☆115Updated this week
- An integrated CGRA design framework☆91Updated 7 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Project repo for the POSH on-chip network generator☆50Updated 7 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆114Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- ☆63Updated 5 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Python wrapper for verilator model☆90Updated last year
- A DSL for Systolic Arrays☆82Updated 6 years ago
- high-performance RTL simulator☆178Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆189Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- ☆50Updated 3 months ago
- Falcon Merlin Compiler☆41Updated 5 years ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆18Updated 9 years ago
- A tool to generate optimized hardware files for univariate functions.☆28Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- ☆15Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- ☆44Updated last year