arcade-lab / tia-infrastructure
☆17Updated 7 years ago
Alternatives and similar repositories for tia-infrastructure:
Users that are interested in tia-infrastructure are comparing it to the libraries listed below
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆26Updated 5 years ago
- Project repo for the POSH on-chip network generator☆44Updated last week
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago
- ☆86Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 3 weeks ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆64Updated this week
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- Python wrapper for verilator model☆81Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆27Updated 5 years ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆15Updated 8 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆60Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- eyeriss-chisel3☆40Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆35Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆76Updated 11 months ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆13Updated last year
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago