sharc-lab / DGNN-BoosterView external linksLinks
☆16Apr 10, 2023Updated 2 years ago
Alternatives and similar repositories for DGNN-Booster
Users that are interested in DGNN-Booster are comparing it to the libraries listed below
Sorting:
- An end-to-end GCN inference accelerator written in HLS☆18Apr 5, 2022Updated 3 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆75Dec 19, 2022Updated 3 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Apr 15, 2022Updated 3 years ago
- ☆37Jan 20, 2022Updated 4 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆22Aug 8, 2022Updated 3 years ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆39Mar 30, 2022Updated 3 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆24Nov 8, 2024Updated last year
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 7 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- NeuraChip Accelerator Simulator☆15Apr 26, 2024Updated last year
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 5 years ago
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆14Nov 19, 2023Updated 2 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28May 11, 2022Updated 3 years ago
- ☆11Feb 11, 2019Updated 7 years ago
- The programming runtime and interfaces for ARENA.☆14Sep 14, 2021Updated 4 years ago
- ☆32Aug 21, 2021Updated 4 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- [SIGMETRICS 2022] One Proxy Device Is Enough for Hardware-Aware Neural Architecture Search☆13Nov 3, 2021Updated 4 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Jan 3, 2022Updated 4 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Jan 2, 2021Updated 5 years ago
- Heterogenous ML accelerator☆20May 5, 2025Updated 9 months ago
- Fast Floating Point Operators for High Level Synthesis☆23Feb 23, 2023Updated 2 years ago
- A graph linear algebra overlay☆51Apr 26, 2023Updated 2 years ago
- ☆18Feb 3, 2022Updated 4 years ago
- pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel stori…☆18Jan 12, 2023Updated 3 years ago
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆19Mar 6, 2021Updated 4 years ago
- A Dataflow library for graph analytics acceleration☆14Dec 15, 2015Updated 10 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- ☆20Sep 17, 2024Updated last year
- [CVPR 2024] Official implementation for "A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network"☆24Dec 5, 2025Updated 2 months ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- mRNA☆26Mar 16, 2021Updated 4 years ago
- Image processing on FPGA using verilog☆26Dec 5, 2022Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Dec 19, 2025Updated last month
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Jul 28, 2021Updated 4 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago