sharc-lab / DGNN-Booster
☆16Updated last year
Alternatives and similar repositories for DGNN-Booster:
Users that are interested in DGNN-Booster are comparing it to the libraries listed below
- An end-to-end GCN inference accelerator written in HLS☆19Updated 2 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆20Updated 4 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆17Updated 2 years ago
- ☆9Updated 2 years ago
- ☆14Updated 5 months ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆13Updated 6 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆31Updated last week
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆3Updated 3 years ago
- ☆25Updated 2 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆17Updated 7 months ago
- A general framework for optimizing DNN dataflow on systolic array☆34Updated 4 years ago
- ☆71Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆69Updated 3 years ago
- ☆26Updated 10 months ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated 11 months ago
- ☆19Updated last year
- ☆10Updated 3 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- HW accelerator mapping optimization framework for in-memory computing☆22Updated last month
- ☆14Updated last year
- ☆11Updated 3 years ago
- ☆11Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆86Updated 5 months ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆11Updated last year
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆48Updated 9 months ago
- A graph linear algebra overlay☆51Updated last year