Xilinx / aie-rtLinks
☆25Updated 3 weeks ago
Alternatives and similar repositories for aie-rt
Users that are interested in aie-rt are comparing it to the libraries listed below
Sorting:
- ☆34Updated 4 years ago
- ☆62Updated 10 months ago
- ☆109Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆74Updated last year
- GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated…☆67Updated last week
- ☆122Updated this week
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆71Updated 4 months ago
- ☆32Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆33Updated last year
- ☆16Updated this week
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Updated last year
- Processing in Memory Emulation☆22Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆70Updated last month
- EQueue Dialect☆41Updated 3 years ago
- agile hardware-software co-design☆52Updated 4 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Updated last year
- ☆42Updated 10 months ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆57Updated last week
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆185Updated 3 weeks ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆39Updated 2 years ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆58Updated 5 months ago
- IREE plugin repository for the AMD AIE accelerator☆119Updated this week