Alternatives and similar repositories for FIR_Filter

Users that are interested in FIR_Filter are comparing it to the libraries listed below

• AbdullahAnsarii / BandPassFilter
  FIR band-pass filter using Verilog HDL.
  ☆12Updated 5 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆56Updated 3 months ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆38Updated 8 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 6 years ago
• xfguo / spi
  SPI Master Core clone from OpenCores
  ☆11Updated 12 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆31Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆30Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆91Updated 3 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆17Updated 5 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆54Updated 4 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆53Updated 4 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆38Updated 10 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆62Updated 3 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆64Updated 3 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆24Updated 7 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆42Updated 2 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆22Updated 6 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆30Updated 5 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago