Xilinx / mlir-xtenLinks
☆16Updated this week
Alternatives and similar repositories for mlir-xten
Users that are interested in mlir-xten are comparing it to the libraries listed below
Sorting:
- ☆62Updated 10 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Updated last month
- ☆60Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆62Updated this week
- CGRA Compilation Framework☆91Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆58Updated 5 months ago
- agile hardware-software co-design☆52Updated 4 years ago
- ☆25Updated 3 weeks ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆18Updated 3 years ago
- ☆109Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆74Updated last year
- Heterogeneous simulator for DECADES Project☆32Updated last year
- HeteroCL-MLIR dialect for accelerator design☆42Updated last year
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆122Updated this week
- EQueue Dialect☆41Updated 3 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆32Updated last year
- ☆42Updated 10 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆33Updated last year
- ☆56Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated 3 weeks ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago