Alternatives and similar repositories for mlir-xten

Users that are interested in mlir-xten are comparing it to the libraries listed below

• Xilinx / aie-rt
  ☆18Updated 2 weeks ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆23Updated 5 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆59Updated 7 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• pc2 / HPCC_FPGA
  A OpenCL-based FPGA benchmark suite for HPC
  ☆32Updated 3 months ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆46Updated 3 years ago
• Xilinx / mlir-air
  ☆97Updated last week
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆90Updated 7 months ago
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆19Updated last year
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆40Updated 7 months ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• arc-research-lab / Aries
  ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)
  ☆26Updated this week
• Xilinx / merlin-compiler
  ☆57Updated last year
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆35Updated 3 weeks ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆38Updated 6 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 4 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆51Updated last month
• union-codesign / union
  ☆14Updated 3 years ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆44Updated last month
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆30Updated 2 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• suchandler96 / gem5-NVDLA
  ☆30Updated last month
• lana555 / dynamatic
  ☆86Updated last year
• StanfordAHA / aha
  ☆58Updated this week
• hngenc / stellar
  ☆27Updated 6 months ago