YuanTingHsieh / ITDPLinks
Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
☆14Updated 7 years ago
Alternatives and similar repositories for ITDP
Users that are interested in ITDP are comparing it to the libraries listed below
Sorting:
- IDEA project source files☆107Updated 9 months ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated 2 weeks ago
- Rsyn – An Extensible Physical Synthesis Framework☆127Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- GPU-based logic synthesis tool☆86Updated last month
- DATC RDF☆50Updated 5 years ago
- EDA physical synthesis optimization kit☆60Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 3 months ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆54Updated 6 months ago
- ☆43Updated 10 months ago
- Artificial Netlist Generator☆39Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆151Updated 3 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆47Updated last year
- The first version of TritonPart☆28Updated last year
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆56Updated 3 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆29Updated 3 years ago
- ☆39Updated 2 years ago
- EPFL logic synthesis benchmarks☆203Updated 3 weeks ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆41Updated last month
- A Standalone Structural Verilog Parser☆96Updated 3 years ago
- UCSD Detailed Router☆90Updated 4 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆51Updated 2 months ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆135Updated 2 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆31Updated 3 weeks ago