YuanTingHsieh / ITDPLinks
Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
☆15Updated 8 years ago
Alternatives and similar repositories for ITDP
Users that are interested in ITDP are comparing it to the libraries listed below
Sorting:
- Collection of digital hardware modules & projects (benchmarks)☆75Updated last month
- Rsyn – An Extensible Physical Synthesis Framework☆136Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆108Updated last year
- Artificial Netlist Generator☆46Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆141Updated 2 years ago
- VLSI EDA Global Router☆79Updated 7 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆141Updated 2 years ago
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 3 years ago
- EDA physical synthesis optimization kit☆64Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆91Updated 8 months ago
- DATC RDF☆50Updated 5 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆60Updated 11 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆167Updated 8 months ago
- IDEA project source files☆111Updated 2 months ago
- UCSD Detailed Router☆94Updated 5 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆61Updated 7 months ago
- GPU-based logic synthesis tool☆97Updated last month
- Open Source Detailed Placement engine☆40Updated 6 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆189Updated 7 months ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆85Updated last year
- DATC Robust Design Flow.☆36Updated 5 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆149Updated 6 months ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆44Updated 7 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆29Updated 5 years ago
- ☆77Updated this week
- ☆41Updated 3 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆60Updated 6 months ago
- ☆15Updated 3 months ago
- Bounded-Skew DME v1.3☆15Updated 7 years ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆76Updated last month