Chenghao-Yang / awesome-ml4lsLinks
Awesome machine learning for logic synthesis
☆26Updated 2 years ago
Alternatives and similar repositories for awesome-ml4ls
Users that are interested in awesome-ml4ls are comparing it to the libraries listed below
Sorting:
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆18Updated last month
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 4 years ago
- Simple Python interface for ABC☆23Updated 2 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆21Updated last year
- ☆15Updated 7 years ago
- ☆28Updated last year
- Research paper based on or related to ABC.☆43Updated last week
- ☆15Updated 2 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 5 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆26Updated last month
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated 8 months ago
- ☆17Updated 2 years ago
- ☆22Updated 11 months ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated 3 weeks ago
- GPU-based logic synthesis tool☆81Updated 10 months ago
- Problems and Results of IWLS 2022 Programming Contest☆19Updated last month
- ☆11Updated 2 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆15Updated 2 years ago
- ☆24Updated last year
- Optimal gate sizing of digital circuits using geometric programming☆11Updated 8 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆22Updated 3 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 4 months ago
- Artificial Netlist Generator☆39Updated last year
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆48Updated 4 months ago
- Logic optimization and technology mapping tool.☆18Updated last year
- ☆29Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆48Updated last week
- DATC Robust Design Flow.☆37Updated 5 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆128Updated 7 months ago
- A logic synthesis tool☆73Updated last month