SJTU-ECTL / GOMIL
GOMIL: Global Optimization of Multiplier by Integer Linear Programming
☆13Updated 3 years ago
Alternatives and similar repositories for GOMIL:
Users that are interested in GOMIL are comparing it to the libraries listed below
- ☆16Updated 3 years ago
- ☆16Updated 4 years ago
- ☆25Updated last year
- ☆15Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆55Updated this week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆47Updated 7 months ago
- ☆59Updated last week
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated 7 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 8 months ago
- This is a python repo for flattening Verilog☆16Updated last month
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 4 months ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆18Updated 11 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆33Updated 3 months ago
- ☆22Updated 10 months ago
- Benchmarks for Approximate Circuit Synthesis☆16Updated 4 years ago
- ☆15Updated 2 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆15Updated 2 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 3 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆29Updated 9 months ago
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆34Updated 2 weeks ago
- ☆31Updated 11 months ago
- An infrastructure for integrated EDA☆39Updated last year
- A hardware synthesis framework with multi-level paradigm☆38Updated 4 months ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆11Updated 2 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆81Updated last week
- DASS HLS Compiler☆29Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year