Alternatives and similar repositories for boom-explorer-public

Users that are interested in boom-explorer-public are comparing it to the libraries listed below

• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 10 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆47Updated 7 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆31Updated 2 years ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆72Updated 6 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆84Updated 4 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆43Updated last year
• pku-dasys / easymac
  ☆18Updated 3 years ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 3 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆82Updated 4 months ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆38Updated 6 months ago
• hngenc / stellar
  ☆32Updated last year
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆84Updated 5 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆62Updated 10 months ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆85Updated 2 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆65Updated 8 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆67Updated 4 years ago
• Yinxiao-Feng / chiplet-network-sim
  ☆55Updated 7 months ago
• mec-UMN / HISIM
  HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…
  ☆62Updated 10 months ago
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆17Updated 2 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆152Updated last week
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆74Updated last year
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• maestro-project / gamma
  ☆42Updated last year
• gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
  A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
  ☆23Updated last year
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆78Updated 7 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 6 months ago
• topanitanw / Cacti-7.0
  ☆24Updated 9 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆74Updated 2 months ago
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆28Updated 4 months ago