Alternatives and similar repositories for SparSynergy

Users that are interested in SparSynergy are comparing it to the libraries listed below

• leesou / H2-LLM-ISCA-2025
  H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
  ☆79Updated 8 months ago
• scalesim-project / scale-sim-v3
  ☆51Updated 3 weeks ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆81Updated 4 months ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆81Updated 9 months ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆107Updated 8 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆69Updated 2 months ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆54Updated 4 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆67Updated 2 weeks ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 5 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆45Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• SET-Scheduling-Project / SoMa-HPCA2025
  ☆25Updated 10 months ago
• CLab-HKUST-GZ / micro58-axcore
  ☆29Updated 2 months ago
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆45Updated last year
• FPSG-UIUC / micro24-fusemax-artifact
  MICRO 2024 Evaluation Artifact for FuseMax
  ☆16Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆73Updated last month
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆28Updated last year
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• sunxt99 / PIMCOMP-NN
  ☆73Updated 10 months ago
• arkhadem / aim_simulator
  A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0
  ☆51Updated 5 months ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆54Updated 2 years ago
• huweim / dataflow_architecture
  Research about dataflow architecture
  ☆12Updated 2 years ago
• hatsu3 / Sanger
  ☆48Updated 4 years ago
• UniNDP-hpca25-ae / UniNDP
  Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"
  ☆50Updated 3 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆61Updated 9 months ago
• wangxy-2000 / pimsim-nn
  ☆58Updated last year
• mec-UMN / HISIM
  HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…
  ☆60Updated 9 months ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆18Updated last year
• PSAL-POSTECH / PyTorchSim
  PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework
  ☆67Updated this week