Alternatives and similar repositories for FSA

Users that are interested in FSA are comparing it to the libraries listed below

• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆36Updated last month
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆94Updated 10 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 5 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆55Updated 3 weeks ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• pulp-platform / ITA
  ☆47Updated 3 months ago
• suchandler96 / gem5-NVDLA
  ☆33Updated 4 months ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆76Updated 6 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆40Updated 6 months ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆66Updated 3 weeks ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 4 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆56Updated 4 months ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆31Updated 2 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆67Updated 3 months ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆77Updated 6 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆81Updated last year
• pulp-platform / fpu
  ☆52Updated 6 years ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆68Updated last year
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆60Updated 4 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆60Updated 9 months ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆36Updated 7 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆60Updated 7 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated last year