Alternatives and similar repositories for LLM4HWDesign_Starting_Toolkit

Users that are interested in LLM4HWDesign_Starting_Toolkit are comparing it to the libraries listed below

• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated 10 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated last month
• ACADLab / SA-DS
  ☆12Updated 11 months ago
• Yu-Maryland / Differentiable_Scheduler_ICML24
  Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.
  ☆21Updated 8 months ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆16Updated 4 years ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆43Updated 7 months ago
• Qimeng-ICT / Qimeng-1
  ☆21Updated 2 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated 2 years ago
• iwls2020-lsml-contest / iwls2020-lsml-contest
  ☆21Updated 2 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆24Updated last month
• milo168 / FPGA25_SAT_Accel
  FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository
  ☆12Updated 4 months ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆21Updated last year
• yaohuicai / smoothe-artifact
  ☆14Updated 8 months ago
• GATECH-EIC / mg-verilog
  ☆46Updated 9 months ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆30Updated 6 months ago
• Entropy-xcy / sns
  ☆18Updated 2 years ago
• icgrp / hipr
  ☆15Updated 2 years ago
• yuzeng2333 / autoGenILA
  Automatic generation of architecture-level models for hardware from its RTL design.
  ☆13Updated 2 years ago
• IPRC-DIP / CodeV
  ☆44Updated last month
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated 9 months ago
• wincle626 / HLS_Legup
  ☆27Updated 7 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆17Updated 3 months ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆25Updated last year