Alternatives and similar repositories for LLM4HWDesign_Starting_Toolkit:

Users that are interested in LLM4HWDesign_Starting_Toolkit are comparing it to the libraries listed below

• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 7 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 2 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆49Updated 2 months ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆24Updated last year
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆17Updated 10 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆15Updated 4 years ago
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆22Updated 2 years ago
• yuzeng2333 / autoGenILA
  Automatic generation of architecture-level models for hardware from its RTL design.
  ☆14Updated last year
• ACADLab / SA-DS
  ☆11Updated 8 months ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆20Updated 8 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆50Updated 5 months ago
• Entropy-xcy / sns
  ☆15Updated 2 years ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆52Updated last year
• Yu-Maryland / Differentiable_Scheduler_ICML24
  Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.
  ☆19Updated 4 months ago
• iwls2020-lsml-contest / iwls2020-lsml-contest
  ☆21Updated 2 years ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆37Updated 3 months ago
• cure-lab / DeepGate2
  ☆14Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 11 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆43Updated 6 months ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆22Updated 3 weeks ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆17Updated 2 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆15Updated last year
• yaoxufeng / RTLRewriter-Bench
  ☆28Updated 10 months ago
• chhzh123 / ptc-tutorial
  PyTorch compilation tutorial covering TorchScript, torch.fx, and Slapo
  ☆18Updated 2 years ago
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆12Updated 6 months ago
• GATECH-EIC / mg-verilog
  ☆40Updated 5 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆25Updated 5 months ago