GATECH-EIC / LLM4HWDesign_Starting_Toolkit
LLM4HWDesign Starting Toolkit
☆17Updated 4 months ago
Alternatives and similar repositories for LLM4HWDesign_Starting_Toolkit:
Users that are interested in LLM4HWDesign_Starting_Toolkit are comparing it to the libraries listed below
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 5 months ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆15Updated 8 months ago
- ☆16Updated 3 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆19Updated 7 months ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated last year
- ☆49Updated 4 months ago
- ACM TODAES Best Paper Award, 2022☆24Updated last year
- Benchmarks for Approximate Circuit Synthesis☆15Updated 4 years ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆35Updated 2 months ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆19Updated 3 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆14Updated last year
- ☆10Updated 6 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- ☆25Updated 9 months ago
- This is a repo to store circuit design datasets☆15Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆41Updated 5 months ago
- ☆14Updated 2 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated last month
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 4 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆28Updated 3 weeks ago
- ☆21Updated 2 years ago
- ☆38Updated 4 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated last month
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 7 months ago
- This is a python repo for flattening Verilog☆15Updated last month