Alternatives and similar repositories for LLM4HWDesign_Starting_Toolkit

Users that are interested in LLM4HWDesign_Starting_Toolkit are comparing it to the libraries listed below

• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆31Updated last year
• ACADLab / SA-DS
  ☆12Updated last year
• iwls2020-lsml-contest / iwls2020-lsml-contest
  ☆21Updated 2 years ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆14Updated 11 months ago
• milo168 / FPGA25_SAT_Accel
  FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository
  ☆13Updated 6 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆53Updated 3 months ago
• GATECH-EIC / mg-verilog
  ☆47Updated 11 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆24Updated 5 months ago
• Yu-Maryland / Differentiable_Scheduler_ICML24
  Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.
  ☆20Updated 10 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 8 months ago
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated 2 years ago
• IPRC-DIP / CodeV
  ☆47Updated 2 weeks ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆33Updated 8 months ago
• Qimeng-ICT / Qimeng-1
  ☆24Updated 4 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• HPAI-BSC / TuRTLe
  TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)
  ☆23Updated 2 weeks ago
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆12Updated last year
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆29Updated 3 years ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• yaohuicai / smoothe-artifact
  ☆16Updated last month
• he-actlab / polymath
  ☆22Updated 7 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• DfX-NYUAD / LLM4IC
  LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
  ☆29Updated last year
• amahzoon / genmul
  ☆17Updated 4 years ago