GATECH-EIC / LLM4HWDesign_Starting_Toolkit
LLM4HWDesign Starting Toolkit
☆17Updated 6 months ago
Alternatives and similar repositories for LLM4HWDesign_Starting_Toolkit:
Users that are interested in LLM4HWDesign_Starting_Toolkit are comparing it to the libraries listed below
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆21Updated 9 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 8 months ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆14Updated 2 years ago
- ☆51Updated 6 months ago
- ☆11Updated 8 months ago
- ☆16Updated 3 years ago
- Benchmarks for Approximate Circuit Synthesis☆16Updated 4 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆18Updated 11 months ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- ☆23Updated this week
- ☆10Updated 5 months ago
- This is a python repo for flattening Verilog☆16Updated 2 weeks ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 3 weeks ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated last year
- A graph linear algebra overlay☆51Updated last year
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆20Updated 5 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆39Updated 4 months ago
- ☆21Updated 2 years ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA☆22Updated 9 months ago
- An HBM FPGA based SpMV Accelerator☆12Updated 7 months ago
- ☆25Updated last year
- ACM TODAES Best Paper Award, 2022☆23Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated 6 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 3 months ago
- This is a repo to store circuit design datasets☆16Updated last year
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆12Updated 7 months ago
- ☆41Updated 6 months ago