jasonlin316 / GCN-Inference-Acceleration-HLS
An end-to-end GCN inference accelerator written in HLS
☆19Updated 3 years ago
Alternatives and similar repositories for GCN-Inference-Acceleration-HLS
Users that are interested in GCN-Inference-Acceleration-HLS are comparing it to the libraries listed below
Sorting:
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆17Updated 2 years ago
- ☆16Updated 2 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- ☆16Updated 7 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆18Updated 9 months ago
- An HBM FPGA based SpMV Accelerator☆12Updated 8 months ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆36Updated 3 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 3 years ago
- NeuraChip Accelerator Simulator☆11Updated last year
- ☆10Updated 2 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆22Updated 6 months ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆72Updated 2 years ago
- ☆16Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆23Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆14Updated 3 years ago
- ☆29Updated 5 months ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated 11 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆51Updated last month
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago