Alternatives and similar repositories for GCN-Inference-Acceleration-HLS

Users that are interested in GCN-Inference-Acceleration-HLS are comparing it to the libraries listed below

• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆42Updated 4 years ago
• Xtra-Computing / ReGraph
  Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines
  ☆22Updated 3 years ago
• pgroupATusc / GraphACT
  Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
  ☆12Updated 5 years ago
• sharc-lab / DGNN-Booster
  ☆16Updated 2 years ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆15Updated last year
• GATECH-EIC / GCoD
  [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design
  ☆38Updated 3 years ago
• lsq314 / SpMM_TCAD
  ☆20Updated last year
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆17Updated last year
• GraphSAINT / GraphACT
  [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…
  ☆19Updated 4 years ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆74Updated 3 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆23Updated last year
• SFU-HiAccel / CHIP-KNN
  [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs
  ☆18Updated last year
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆20Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆46Updated 2 years ago
• UCLA-VAST / splag
  Accelerating SSSP for power-law graphs using an FPGA.
  ☆23Updated 3 years ago
• Yinxiao-Feng / chiplet-network-sim
  ☆55Updated 7 months ago
• CGCL-codes / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆15Updated last year
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆21Updated 9 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• ic-lab-duth / FusedGCN4HLS
  Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
  ☆23Updated 3 years ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆22Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 4 years ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• hngenc / stellar
  ☆32Updated last year
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆22Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆46Updated 3 years ago
• sparsh0mittal / destiny_3d_cache
  Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…
  ☆25Updated last year