Alternatives and similar repositories for cva6-sdk

Users that are interested in cva6-sdk are comparing it to the libraries listed below

• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆172Updated 7 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated 2 weeks ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆252Updated 2 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆89Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆99Updated 2 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆154Updated 8 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆220Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated this week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆135Updated 2 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆171Updated 3 weeks ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆183Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 4 years ago
• sparcians / map
  Modeling Architectural Platform
  ☆197Updated this week
• chipsalliance / uvm-verilator
  ☆97Updated last year
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆102Updated 6 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆122Updated 4 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆180Updated 8 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆159Updated 5 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year