Alternatives and similar repositories for cva6-sdk:

Users that are interested in cva6-sdk are comparing it to the libraries listed below

• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆190Updated 9 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆73Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆132Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆91Updated 3 weeks ago
• riscv / riscv-CMOs
  ☆86Updated 2 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 9 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆195Updated 2 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆171Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆71Updated last week
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆50Updated 3 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆83Updated last month
• chipsalliance / uvm-verilator
  ☆92Updated last year
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆166Updated 4 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆17Updated 2 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆61Updated 11 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆89Updated 2 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆242Updated 6 months ago
• ucb-bar / sha3
  ☆79Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆57Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆172Updated 2 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆61Updated 2 weeks ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆38Updated last month
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 6 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆143Updated 10 months ago