cfelton / rhea
A collection of MyHDL cores and tools for complex digital circuit design
☆86Updated 6 years ago
Alternatives and similar repositories for rhea:
Users that are interested in rhea are comparing it to the libraries listed below
- Python tools for Vivado Projects☆73Updated 6 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 2 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 3 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆121Updated 8 years ago
- FuseSoC standard core library☆134Updated last month
- A utility for Composing FPGA designs from Peripherals☆178Updated 4 months ago
- LIB:Library for interacting with an FPGA over USB☆84Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Utilities for MyHDL☆18Updated last year
- ☆131Updated 4 months ago
- The original high performance and small footprint system-on-chip based on Migen™☆326Updated last month
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 4 years ago
- Yet Another RISC-V Implementation☆93Updated 7 months ago
- Core description files for FuseSoC☆124Updated 4 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆80Updated 5 years ago
- A wishbone controlled scope for FPGA's☆81Updated last year
- An Open Source configuration of the Arty platform☆130Updated last year
- a playground for xilinx zynq fpga experiments☆48Updated 6 years ago
- ☆59Updated last year
- Verification Utilities for MyHDL☆17Updated last year
- A very simple UART implementation in MyHDL☆17Updated 10 years ago
- A VHDL frontend for Yosys☆102Updated 8 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 2 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- Collection of open-source peripherals in Verilog☆174Updated 3 years ago
- LatticeMico32 soft processor☆105Updated 10 years ago
- Verilog wishbone components☆114Updated last year
- Sample minimal Vivado project for Parallella FPGA☆42Updated 8 years ago
- Generic Logic Interfacing Project☆46Updated 4 years ago