Alternatives and similar repositories for rhea

Users that are interested in rhea are comparing it to the libraries listed below

• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 6 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 3 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• forflo / yodl
  A VHDL frontend for Yosys
  ☆102Updated 8 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 6 months ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆106Updated 10 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆123Updated 8 years ago
• ldoolitt / vhd2vl
  ☆133Updated 6 months ago
• makestuff / libfpgalink
  LIB:Library for interacting with an FPGA over USB
  ☆84Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆143Updated 3 weeks ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆46Updated 4 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 6 years ago
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆49Updated 6 years ago
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆328Updated last month
• andrecp / myhdl_simple_uart
  A very simple UART implementation in MyHDL
  ☆17Updated 10 years ago
• cfelton / gizflo
  that FPGA flow
  ☆9Updated 9 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 4 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆129Updated last year
• hgomersall / Veriutils
  Verification Utilities for MyHDL
  ☆17Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• cyrozap / python-bsdl-parser
  A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files
  ☆25Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated 3 weeks ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 8 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆88Updated 6 years ago
• jck / riscv
  ☆19Updated last year
• mcmayer / iCE40
  Lattice iCE40 FPGA experiments - Work in progress
  ☆105Updated 3 years ago