jck / uhdl
Utilities for MyHDL
☆17Updated last year
Alternatives and similar repositories for uhdl:
Users that are interested in uhdl are comparing it to the libraries listed below
- A very simple UART implementation in MyHDL☆17Updated 10 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆20Updated 9 years ago
- Verification Utilities for MyHDL☆17Updated last year
- Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.☆40Updated 11 months ago
- MyHDL hardware design language encased in the tasty PygMyHDL wrapper.☆19Updated 2 years ago
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Updated 12 years ago
- A tool for merging the MyHDL workflow with Vivado☆19Updated 4 years ago
- Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL☆35Updated 6 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆85Updated 6 years ago
- Extensible FPGA control platform☆55Updated last year
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 4 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- CLI for WaveDrom☆61Updated 10 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- FuseSoc Verification Automation☆22Updated 2 years ago
- Digital Circuit rendering engine☆36Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆22Updated 3 years ago
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Updated 3 months ago
- An abstract language model of VHDL written in Python.☆50Updated last week
- Yosys Plugins☆21Updated 5 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 3 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆36Updated 4 years ago
- ☆30Updated 3 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 7 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- VHDL-2008 Support Library☆57Updated 8 years ago