Alternatives and similar repositories for myhdl-resources

Users that are interested in myhdl-resources are comparing it to the libraries listed below

• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆72Updated 6 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆146Updated 2 years ago
• ldoolitt / vhd2vl
  ☆138Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• kevinpt / symbolator
  HDL symbol generator
  ☆200Updated 2 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆221Updated 3 weeks ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆81Updated 2 weeks ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆118Updated 4 years ago
• idea-fasoc / fasoc
  ☆57Updated 2 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆65Updated 3 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆65Updated 2 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆83Updated 5 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated last week
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆96Updated 4 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆73Updated last week
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆61Updated 2 years ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 3 weeks ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆70Updated last month
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last month
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆90Updated 10 months ago