Alternatives and similar repositories for myhdl-resources:

Users that are interested in myhdl-resources are comparing it to the libraries listed below

• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆114Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆177Updated 4 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆210Updated 5 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated this week
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 9 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆133Updated 3 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• ldoolitt / vhd2vl
  ☆131Updated 4 months ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 6 years ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆93Updated 6 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆189Updated 2 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆103Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 2 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆91Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆176Updated last week
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆58Updated 5 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆83Updated 9 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated last week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆60Updated last week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆120Updated this week
• Digilent / digilent-vivado-scripts
  ☆69Updated last month
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆147Updated 5 months ago
• pieter3d / simview
  ☆77Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 7 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago