Alternatives and similar repositories for myhdl-resources:

Users that are interested in myhdl-resources are comparing it to the libraries listed below

• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆173Updated 3 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆129Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 8 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 5 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆138Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆113Updated last month
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆128Updated last year
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆57Updated 4 months ago
• pieter3d / simview
  ☆77Updated last year
• kevinpt / symbolator
  HDL symbol generator
  ☆189Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆90Updated 6 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆110Updated 3 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆80Updated 5 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆94Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated 2 weeks ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆146Updated last week
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 8 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆119Updated 2 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆163Updated last month
• ldoolitt / vhd2vl
  ☆129Updated 3 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆60Updated 2 weeks ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆39Updated last year