kdurant / axi-ddr3View external linksLinks
学习AXI接口,以及xilinx DDR3 IP使用
☆40Mar 6, 2017Updated 8 years ago
Alternatives and similar repositories for axi-ddr3
Users that are interested in axi-ddr3 are comparing it to the libraries listed below
Sorting:
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- ☆27Jun 12, 2022Updated 3 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆34Oct 23, 2025Updated 3 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 13 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- ☆27May 11, 2021Updated 4 years ago
- Gigabit Ethernet UDP communication driver☆80Jul 26, 2019Updated 6 years ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆35Sep 17, 2019Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- minimal code to access ps DDR from PL☆22Oct 18, 2019Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- SDRAM controller with AXI4 interface☆101Aug 8, 2019Updated 6 years ago
- Repository gathering basic modules for CDC purpose☆58Dec 31, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Verification IP for UART protocol☆23Aug 3, 2020Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆44Aug 18, 2014Updated 11 years ago
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated last year
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆22Sep 2, 2023Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆84Aug 9, 2020Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- 使用verilog编写sdram控制器☆12Jun 22, 2019Updated 6 years ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- ☆45Apr 11, 2017Updated 8 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago