kdurant / axi-ddr3Links
学习AXI接口,以及xilinx DDR3 IP使用
☆37Updated 8 years ago
Alternatives and similar repositories for axi-ddr3
Users that are interested in axi-ddr3 are comparing it to the libraries listed below
Sorting:
- ☆36Updated 9 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆25Updated 4 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- AXI Interconnect☆49Updated 3 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- ☆51Updated 2 years ago
- ☆20Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- AHB DMA 32 / 64 bits☆55Updated 10 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆72Updated last year
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 weeks ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- Implementation of the PCIe physical layer☆40Updated 2 weeks ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- AXI总线连接器☆97Updated 5 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago