kdurant / axi-ddr3Links
学习AXI接口,以及xilinx DDR3 IP使用
☆37Updated 8 years ago
Alternatives and similar repositories for axi-ddr3
Users that are interested in axi-ddr3 are comparing it to the libraries listed below
Sorting:
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AXI Interconnect☆49Updated 3 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- ☆20Updated 2 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- ☆25Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆36Updated 9 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- Implementation of the PCIe physical layer☆42Updated last month
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- ☆55Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 10 months ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- AXI总线连接器☆98Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆73Updated last year
- DOULOS Easier UVM Code Generator☆34Updated 8 years ago