kdurant / axi-ddr3
学习AXI接口,以及xilinx DDR3 IP使用
☆36Updated 7 years ago
Alternatives and similar repositories for axi-ddr3:
Users that are interested in axi-ddr3 are comparing it to the libraries listed below
- AXI Interconnect☆47Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- ☆35Updated 9 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- ☆23Updated 3 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- ☆16Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆28Updated 2 years ago
- Implementation of the PCIe physical layer☆32Updated this week
- Generic AXI to AHB bridge☆16Updated 10 years ago
- PCIE 5.0 Graduation project (Verification Team)☆57Updated 11 months ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆20Updated 3 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- Verification IP for APB protocol☆56Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆52Updated 8 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- an open source uvm verification platform for e200 (riscv)☆26Updated 6 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- 视频旋转(2019FPGA大赛)☆30Updated 4 years ago
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆24Updated 4 years ago
- 帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目☆32Updated 2 years ago
- Must-have verilog systemverilog modules☆28Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆22Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆30Updated 2 years ago
- ☆20Updated 5 years ago