学习AXI接口，以及xilinx DDR3 IP使用
☆40Mar 6, 2017Updated 9 years ago
Alternatives and similar repositories for axi-ddr3
Users that are interested in axi-ddr3 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- ☆16May 6, 2026Updated 3 months ago
- An AXI DDR3 SDRAM controller for FPGA☆50Dec 30, 2023Updated 2 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- DDR2 memory controller written in Verilog☆85Feb 28, 2012Updated 14 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- AXI Interconnect☆58Aug 20, 2021Updated 4 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- SDRAM controller with AXI4 interface☆108Aug 8, 2019Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- ☆27Jun 12, 2022Updated 4 years ago
- Gigabit Ethernet UDP communication driver☆84Jul 26, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- ☆19Aug 22, 2022Updated 3 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆35Sep 17, 2019Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆87Aug 9, 2020Updated 6 years ago
- 使用verilog编写sdram控制器☆13Jun 22, 2019Updated 7 years ago
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆19Oct 24, 2014Updated 11 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。☆221Sep 15, 2023Updated 2 years ago
- ☆82Feb 4, 2021Updated 5 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- minimal code to access ps DDR from PL☆23Oct 18, 2019Updated 6 years ago
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- AMBA bus lecture material☆548Jan 21, 2020Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆36Mar 13, 2025Updated last year
- fpga跑sobel识别算法☆48Mar 15, 2021Updated 5 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆624Oct 10, 2021Updated 4 years ago
- ☆30May 11, 2021Updated 5 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- 七路图像在FPGA中实现拼接，代码会不断添加进来。☆29Aug 17, 2021Updated 5 years ago
- 用Altera FPGA芯片自制CPU☆42Aug 10, 2014Updated 12 years ago