kdurant / axi-ddr3
学习AXI接口,以及xilinx DDR3 IP使用
☆35Updated 7 years ago
Alternatives and similar repositories for axi-ddr3:
Users that are interested in axi-ddr3 are comparing it to the libraries listed below
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆35Updated 9 years ago
- ☆24Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- Implementation of the PCIe physical layer☆33Updated last month
- Generic AXI to AHB bridge☆16Updated 10 years ago
- FFT implement by verilog_测试验证已通过☆53Updated 8 years ago
- ☆16Updated 2 years ago
- ☆20Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆29Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- DDR3 function verification environment in UVM☆23Updated 6 years ago
- ☆40Updated 2 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- 视频旋转(2019FPGA大赛)☆31Updated 4 years ago
- AXI总线连接器☆94Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆61Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Verification IP for APB protocol☆57Updated 4 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago