Alternatives and similar repositories for tree-core-cpu:

Users that are interested in tree-core-cpu are comparing it to the libraries listed below

• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 2 months ago
• pulp-platform / fpu
  ☆42Updated 6 years ago
• OSCPU / ysyxSoC
  ☆82Updated last month
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated last week
• OSCPU / chisel-playground
  ☆63Updated last month
• CherrySprings / CherrySprings
  ☆17Updated last year
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆91Updated last month
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• lizhirui / DreamCoreV2
  ☆22Updated last year
• sequencer / arithmetic
  ☆32Updated last week
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆24Updated this week
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆60Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• OSCPU / yosys-sta
  ☆62Updated 3 months ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆16Updated this week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 10 months ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆52Updated 7 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 5 months ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆51Updated 4 years ago
• lingscale / cc01
  ☆31Updated 2 weeks ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆38Updated 2 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆97Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 8 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆56Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago