microdynamics-cpu / tree-core-cpuLinks
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
☆40Updated last year
Alternatives and similar repositories for tree-core-cpu
Users that are interested in tree-core-cpu are comparing it to the libraries listed below
Sorting:
- An almost empty chisel project as a starting point for hardware design☆31Updated 4 months ago
- ☆36Updated 6 years ago
- ☆31Updated 2 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆101Updated 3 months ago
- ☆49Updated 6 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- ☆86Updated last month
- ☆22Updated 2 years ago
- ☆64Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 3 weeks ago
- ☆67Updated 3 months ago
- ☆18Updated 2 years ago
- ☆42Updated 3 years ago
- ☆64Updated last month
- eyeriss-chisel3☆40Updated 3 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆56Updated 3 years ago
- ☆28Updated 4 years ago
- Pick your favorite language to verify your chip.☆49Updated last week
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- ☆33Updated 2 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆59Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 9 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- ☆66Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago