microdynamics-cpu / tree-core-cpuLinks
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
☆43Updated last year
Alternatives and similar repositories for tree-core-cpu
Users that are interested in tree-core-cpu are comparing it to the libraries listed below
Sorting:
- ☆37Updated 6 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated 8 months ago
- ☆56Updated 6 years ago
- Pick your favorite language to verify your chip.☆70Updated last week
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- ☆67Updated 8 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆64Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- ☆88Updated 3 weeks ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆116Updated 8 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- ☆44Updated 3 years ago
- Advanced Architecture Labs with CVA6☆68Updated last year
- ☆22Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆112Updated 3 years ago
- ☆83Updated 6 months ago
- ☆30Updated 2 months ago
- ☆18Updated 2 years ago
- XiangShan Frontend Develop Environment☆68Updated last month
- ☆30Updated 7 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆43Updated 3 weeks ago
- SpinalHDL-tutorial based on Jupyter Notebook☆141Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆177Updated last month
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- ☆53Updated 6 months ago
- "aura" my super-scalar O3 cpu core☆24Updated last year