Alternatives and similar repositories for tree-core-cpu

Users that are interested in tree-core-cpu are comparing it to the libraries listed below

• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆31Updated 4 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• lingscale / cc01
  ☆31Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆101Updated 3 months ago
• pulp-platform / fpu
  ☆49Updated 6 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• OSCPU / ysyxSoC
  ☆86Updated last month
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 3 weeks ago
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• OSCPU / yosys-sta
  ☆64Updated last month
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆56Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆28Updated 4 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆49Updated last week
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• sequencer / arithmetic
  ☆33Updated 2 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆59Updated 3 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated 9 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆27Updated 2 weeks ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 10 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆134Updated 2 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago