常用Verilog模块
☆20Mar 3, 2020Updated 6 years ago
Alternatives and similar repositories for Verilog_Module
Users that are interested in Verilog_Module are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 视频旋转（2019FPGA大赛）☆41May 5, 2020Updated 5 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- ☆10Aug 30, 2024Updated last year
- GUI for SymbiYosys☆17Oct 13, 2025Updated 6 months ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 🧛🏻♂️ Dark theme for Vivado☆21Jun 27, 2023Updated 2 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- H264视频解码verilog实现☆88Aug 11, 2017Updated 8 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 7 years ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 4 months ago
- 基于Verilog实现的串口发送程序，带奇偶校验位。☆12Aug 23, 2019Updated 6 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- open cv software isp study☆17Nov 9, 2020Updated 5 years ago
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆12Jan 15, 2022Updated 4 years ago
- Rust unsafe bindings for Vid API (Hyper-V)☆23Feb 23, 2025Updated last year
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 5 years ago
- ☆13May 21, 2019Updated 6 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- 《winsows内核安全与驱动开发》，谭文，陈铭霖等著。配套光盘example。现在还配光盘实在是浪费啊...☆24Dec 18, 2016Updated 9 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 3 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- ☆14Feb 24, 2025Updated last year
- 云崽qq机器人的chatgpt插件-to派蒙☆14Updated this week
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- USB2.0 Verilog☆20Apr 21, 2019Updated 7 years ago
- ☆13Feb 28, 2016Updated 10 years ago
- Make Vim complete like a modern editor - does the right thing. Works with Ultisnips and neocomplete.☆20Apr 15, 2017Updated 9 years ago
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆25Dec 10, 2019Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆14Nov 11, 2015Updated 10 years ago
- 这里是 Yunzai-Bot 的扩展插件库☆10Aug 12, 2024Updated last year
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 10 years ago
- EBAZ4205 and AD9226 as a 0-32 MHz radio spectrum viewer☆16Dec 8, 2022Updated 3 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago