CSY-tvgo / YADAN-DocsLinks
RISC-V YADAN Core, YADAN SoC, YADAN Board's Documentation, designed for engineering education. // 鸭蛋的文档。
☆17Updated 8 months ago
Alternatives and similar repositories for YADAN-Docs
Users that are interested in YADAN-Docs are comparing it to the libraries listed below
Sorting:
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆83Updated 3 years ago
- RV32I Open Source GPU☆14Updated 4 years ago
- 8051 core☆107Updated 11 years ago
- Learn Verilog☆35Updated 5 months ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 4 years ago
- Linux0.11 with MMU for K210(RISC-V) Version☆89Updated 5 years ago
- 用Altera FPGA芯片自制CPU☆41Updated 11 years ago
- Kendryte K230 SDK Docs☆117Updated last month
- sipeed wiki:https://wiki.sipeed.com☆140Updated this week
- ☆64Updated 8 months ago
- A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit.☆157Updated 2 years ago
- Embedded libc,especially for RISC-V.☆38Updated 2 weeks ago
- GoWin FPGA implement nes/fc☆15Updated 2 years ago
- OpenNNA2.0,一个基于C语言(C99)的开源神经网络推理框架☆91Updated 2 years ago
- ☆84Updated 2 months ago
- 使用 C++23 从零实现的 RISC-V 模拟器☆33Updated 8 months ago
- LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.☆17Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆111Updated 3 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated 2 years ago
- 基于ALINX-AX7020平台的Linux驱动开发学习。☆49Updated 5 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆38Updated 4 years ago
- DEPRECATED: Please update to risc-none-elf-gcc-xpack☆125Updated 2 years ago
- Community's fork of Loongson PMON bootloader☆31Updated last year
- ☆14Updated 5 years ago
- ☆11Updated 6 months ago
- The demo projects for Allwinner D1 SBC☆24Updated 4 years ago
- LicheeTang 蜂鸟E203 Core☆198Updated 6 years ago
- ☆37Updated last year
- A lightweight IDE that supports verilog simulation and RISC-V code compilation☆54Updated 3 years ago
- riscv资料、论文等☆143Updated 6 years ago