CSY-tvgo / YADAN-DocsLinks
RISC-V YADAN Core, YADAN SoC, YADAN Board's Documentation, designed for engineering education. // 鸭蛋的文档。
☆17Updated 11 months ago
Alternatives and similar repositories for YADAN-Docs
Users that are interested in YADAN-Docs are comparing it to the libraries listed below
Sorting:
- ☆64Updated 11 months ago
- A lightweight IDE that supports verilog simulation and RISC-V code compilation☆54Updated 3 years ago
- 8051 core☆109Updated 11 years ago
- OpenNNA2.0,一个基于C语言(C99)的开源神经网络推理框架☆92Updated 2 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Updated 4 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Updated 2 years ago
- GoWin FPGA implement nes/fc☆14Updated 2 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 5 years ago
- 《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆132Updated 2 weeks ago
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆87Updated 3 years ago
- ☆10Updated 8 months ago
- RV32I Open Source GPU☆14Updated 4 years ago
- ☆32Updated last week
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit.☆157Updated 3 years ago
- ☆39Updated 5 years ago
- ☆30Updated 9 months ago
- Peripheral Interface of FPGA☆41Updated 4 years ago
- LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.☆17Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- sipeed wiki:https://wiki.sipeed.com☆143Updated last week
- ☆87Updated last week
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Ubuntu 20.04 Desktop Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆14Updated 4 years ago
- Linux capable RISC-V SoC designed to be readable and useful.☆154Updated last week
- Linux0.11 with MMU for K210(RISC-V) Version☆90Updated 5 years ago
- ☆37Updated 7 years ago
- 用Altera FPGA芯片自制CPU☆43Updated 11 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year