yuhsuan-t / NPU-ArchitectureLinks
CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
☆19Updated 8 years ago
Alternatives and similar repositories for NPU-Architecture
Users that are interested in NPU-Architecture are comparing it to the libraries listed below
Sorting:
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆34Updated 6 years ago
- ☆20Updated 2 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- ☆25Updated 4 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆12Updated 2 years ago
- AIChip 2021 project, NCKU☆18Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 5 months ago
- ☆10Updated 4 years ago
- ☆20Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- DMA controller for CNN accelerator☆13Updated 8 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- ☆14Updated 2 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 3 years ago
- ☆12Updated 9 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago