yuhsuan-t / NPU-ArchitectureLinks
CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
☆19Updated 8 years ago
Alternatives and similar repositories for NPU-Architecture
Users that are interested in NPU-Architecture are comparing it to the libraries listed below
Sorting:
- verification of simple axi-based cache☆18Updated 6 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- ☆12Updated 10 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 11 months ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- ☆26Updated 4 years ago
- ☆38Updated 6 years ago
- ☆13Updated 9 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆31Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- Design and UVM-TB of RISC -V Microprocessor☆30Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 6 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- EE577b-Course-Project☆19Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- ☆16Updated 6 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆17Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- UVM resource from github, run simulation use YASAsim flow☆31Updated 5 years ago
- ☆20Updated 3 years ago