Alternatives and similar repositories for starship

Users that are interested in starship are comparing it to the libraries listed below

• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆171Updated this week
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆77Updated this week
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆221Updated 2 months ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆78Updated 5 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆265Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• OSCPU / chisel-playground
  ☆71Updated this week
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated this week
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆60Updated 2 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• OSCPU / ysyxSoC
  ☆92Updated 4 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆160Updated last year
• OSCPU / yosys-sta
  ☆90Updated 2 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆225Updated 2 months ago
• OpenXiangShan / GEM5
  ☆123Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆192Updated 2 years ago
• ucb-bar / sha3
  ☆82Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆211Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆195Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆118Updated 2 months ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆105Updated 7 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆223Updated 5 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆73Updated 2 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 4 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year