sycuricon / starshipLinks
Run rocket-chip on FPGA
☆68Updated 7 months ago
Alternatives and similar repositories for starship
Users that are interested in starship are comparing it to the libraries listed below
Sorting:
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- Comment on the rocket-chip source code☆179Updated 6 years ago
- A dynamic verification library for Chisel.☆151Updated 7 months ago
- ☆36Updated 6 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- ☆86Updated last month
- ☆68Updated 4 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆146Updated this week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 5 years ago
- ☆163Updated last month
- Chisel Learning Journey☆109Updated 2 years ago
- Pure digital components of a UCIe controller☆63Updated this week
- SpinalHDL-tutorial based on Jupyter Notebook☆138Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆203Updated 2 weeks ago
- ☆72Updated 2 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- ☆42Updated 3 years ago
- ☆64Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆66Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Chisel examples and code snippets☆254Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆214Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- Open-source high-performance non-blocking cache☆83Updated 3 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆202Updated last month
- Open source high performance IEEE-754 floating unit☆75Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆157Updated last week
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year