Alternatives and similar repositories for starship

Users that are interested in starship are comparing it to the libraries listed below

• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆134Updated 2 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 7 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆146Updated this week
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• RV-BOSC / OpenNoC
  ☆163Updated last month
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆63Updated this week
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆203Updated 2 weeks ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆66Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆254Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆214Updated 4 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 11 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆83Updated 3 weeks ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆202Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆75Updated last year
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆157Updated last week
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year