sycuricon / starshipLinks
Run rocket-chip on FPGA
☆76Updated last month
Alternatives and similar repositories for starship
Users that are interested in starship are comparing it to the libraries listed below
Sorting:
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Modern co-simulation framework for RISC-V CPUs☆166Updated this week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆218Updated last month
- Chisel Learning Journey☆111Updated 2 years ago
- ☆69Updated 11 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- XiangShan Frontend Develop Environment☆68Updated last week
- Pick your favorite language to verify your chip.☆75Updated last week
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编 程语言话题 ( Writing Blogs using …☆78Updated 5 years ago
- Chisel examples and code snippets☆265Updated 3 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- A dynamic verification library for Chisel.☆159Updated last year
- ☆122Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆91Updated 3 months ago
- ☆191Updated 2 years ago
- ☆89Updated last month
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆223Updated 2 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.