sycuricon / starshipLinks
Run rocket-chip on FPGA
☆76Updated last month
Alternatives and similar repositories for starship
Users that are interested in starship are comparing it to the libraries listed below
Sorting:
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Modern co-simulation framework for RISC-V CPUs☆165Updated this week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month
- Chisel examples and code snippets☆263Updated 3 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- Pick your favorite language to verify your chip.☆73Updated 2 weeks ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- A dynamic verification library for Chisel.☆159Updated last year
- XiangShan Frontend Develop Environment☆68Updated 2 weeks ago
- RISC-V Torture Test☆204Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆190Updated 2 years ago
- ☆68Updated 10 months ago
- ☆91Updated 2 months ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆78Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆224Updated last month
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆76Updated 2 weeks ago
- Documentation for RISC-V Spike☆105Updated 7 years ago
- ☆87Updated last month
- ☆117Updated this week
- Open source high performance IEEE-754 floating unit☆86Updated last year
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆56Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- chipyard in mill :P☆77Updated 2 years ago
- Open-source high-performance non-blocking cache☆92Updated 2 weeks ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆191Updated last year