a training-target implementation of rv32im, designed to be simple and easy to understand
☆60Dec 27, 2021Updated 4 years ago
Alternatives and similar repositories for Cookabarra
Users that are interested in Cookabarra are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 4 years ago
- ☆10Feb 8, 2023Updated 3 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- 32-bit Superscalar RISC-V CPU☆1,324Sep 18, 2021Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated 2 years ago
- Simple UVM testbench development using the uvmtb_template files☆27Jan 16, 2025Updated last year
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆16Nov 23, 2018Updated 7 years ago
- SystemVerilog implemention of the TAGE branch predictor☆15May 26, 2021Updated 5 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆13Oct 20, 2021Updated 5 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆40Mar 13, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆251Updated this week
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆16Dec 4, 2025Updated 10 months ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆36May 17, 2026Updated 5 months ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆43Jan 2, 2022Updated 4 years ago
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆15Jan 30, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RV64emu is a riscv64 emulator written in rust,can run linux !☆23Oct 5, 2024Updated 2 years ago