Alternatives and similar repositories for DandRiscvSoC

Users that are interested in DandRiscvSoC are comparing it to the libraries listed below

• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆25Updated 4 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆67Updated 6 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆45Updated 2 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 2 years ago
• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆39Updated 4 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆59Updated 2 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆43Updated 11 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated 3 weeks ago
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆47Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• Nuclei-Software / e603_hbird
  RV64GC Linux Capable RISC-V Core
  ☆48Updated 2 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆113Updated 3 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated 2 weeks ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆133Updated 5 years ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆33Updated 5 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆18Updated 6 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆84Updated 7 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• ucb-bar / uciedigital
  An open-source UCIe controller implementation
  ☆80Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆87Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆189Updated 3 months ago
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆51Updated 2 years ago
• fayalalebrun / awesome-spinalhdl
  List of SpinalHDL projects, libraries, and learning resources.
  ☆24Updated 8 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago