This repository contains the design files of RISC-V Pipeline Core
☆69May 11, 2023Updated 2 years ago
Alternatives and similar repositories for RISCV_Pipeline_Core
Users that are interested in RISCV_Pipeline_Core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of 5 Stage 32I RISC V Pipeline Processor.☆20Sep 6, 2024Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆63May 8, 2021Updated 4 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Simulation projects on VLSI design.☆14Apr 6, 2021Updated 4 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆17Jan 28, 2022Updated 4 years ago
- Basic RISC-V Test SoC☆181Apr 7, 2019Updated 6 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆60Jul 5, 2024Updated last year
- A web-based graphical simulator of a simple 32-bit, single-cycle implementation of RISC-V☆26Mar 16, 2025Updated last year
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 8 years ago
- ☆14Mar 9, 2026Updated 2 weeks ago
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated last week
- Pipelined RISC-V RV32I Core in Verilog☆41Apr 9, 2023Updated 2 years ago
- ☆23Mar 12, 2026Updated last week
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆121Dec 17, 2023Updated 2 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆35Oct 29, 2023Updated 2 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆36Mar 25, 2020Updated 5 years ago
- Implementation of RISC-V RV32I☆28Aug 30, 2022Updated 3 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 5 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆28Oct 31, 2021Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆140Oct 2, 2025Updated 5 months ago
- This script generates and analyzes prefix tree adders.☆39Apr 9, 2021Updated 4 years ago
- Mirror of the now discontinued ORCA RISC-V processor from VectorBlox.☆10Feb 11, 2020Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- XCrypto: a cryptographic ISE for RISC-V☆92Jan 5, 2023Updated 3 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- Pipeline FFT Implementation in Verilog HDL☆165Apr 14, 2019Updated 6 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆128May 14, 2022Updated 3 years ago
- A Single Cycle Risc-V 32 bit CPU☆68Jan 14, 2026Updated 2 months ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- A tiny RISC-V instruction decoder and instruction set simulator☆35Oct 24, 2025Updated 5 months ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆13Jun 25, 2025Updated 8 months ago
- ☆15May 8, 2018Updated 7 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Feb 25, 2026Updated 3 weeks ago