merldsu / RISCV_Pipeline_Core

Related projects ⓘ

Alternatives and complementary repositories for RISCV_Pipeline_Core

• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆35Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆83Updated 4 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆72Updated 12 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆30Updated 4 months ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆110Updated 6 years ago
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆20Updated 3 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆90Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆121Updated 5 months ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆28Updated 10 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆57Updated 3 weeks ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆68Updated 6 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆117Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆66Updated 6 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆29Updated 2 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆80Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆109Updated 4 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆70Updated 5 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆45Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆127Updated 8 years ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆125Updated 2 years ago
• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆49Updated 2 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆157Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆67Updated 10 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆136Updated 2 weeks ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆82Updated 4 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆142Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆78Updated 5 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year