NAvi349 / riscv-procLinks
32-bit 5-Stage Pipelined RISC V RV32I Core
☆53Updated last year
Alternatives and similar repositories for riscv-proc
Users that are interested in riscv-proc are comparing it to the libraries listed below
Sorting:
- A collection of commonly asked RTL design interview questions☆34Updated 8 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆65Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆85Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆91Updated 6 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆136Updated 5 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆25Updated last month
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆21Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆34Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆112Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 3 years ago
- ☆15Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆119Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆96Updated 2 years ago
- ☆13Updated 6 months ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- ☆48Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- ☆16Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 10 months ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Simple cache design implementation in verilog☆50Updated last year
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆108Updated 9 months ago
- Architectural design of data router in verilog☆30Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago