NAvi349 / riscv-proc

Related projects: ⓘ

• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆31Updated 4 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆20Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆60Updated 6 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆47Updated last year
• Vidhi24-hub / 100daysofrtl
  ☆16Updated 5 months ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆26Updated last year
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆41Updated 5 months ago
• psnjk / SimpleCache
  Simple cache design implementation in verilog
  ☆40Updated 9 months ago
• sudhamshu091 / RISC-Pipelined-Processor-32-bit-Verilog
  Simple Pipelined 32 bit RISC Processor
  ☆13Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆24Updated 5 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆65Updated 5 years ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆11Updated 4 months ago
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆18Updated 6 years ago
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆23Updated 2 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆12Updated 10 months ago
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆18Updated 3 years ago
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆26Updated 4 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆20Updated 2 years ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆10Updated 4 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆112Updated 3 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆82Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆13Updated 6 months ago
• shubhi704 / APB-Protocol
  ☆35Updated 3 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆16Updated 3 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆32Updated 8 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆11Updated 3 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆26Updated 4 years ago
• Juanx65 / RISC-V
  Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
  ☆11Updated last week
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆41Updated 2 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆71Updated 2 years ago