NAvi349 / riscv-proc
32-bit 5-Stage Pipelined RISC V RV32I Core
☆39Updated 8 months ago
Alternatives and similar repositories for riscv-proc:
Users that are interested in riscv-proc are comparing it to the libraries listed below
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆56Updated 2 years ago
- ☆12Updated 3 weeks ago
- ☆40Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- ☆16Updated 11 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆34Updated 2 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆22Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 6 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆81Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆33Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆16Updated 10 months ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- ☆14Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆50Updated last year
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆136Updated 3 weeks ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆67Updated last year
- ☆16Updated last year
- Simple cache design implementation in verilog☆44Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- ☆31Updated 5 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆18Updated 6 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆44Updated last year
- AXI Interconnect☆47Updated 3 years ago