Jash-2000 / Analog-and-Digital-VLSI-DesignLinks
Simulation projects on VLSI design.
☆11Updated 4 years ago
Alternatives and similar repositories for Analog-and-Digital-VLSI-Design
Users that are interested in Analog-and-Digital-VLSI-Design are comparing it to the libraries listed below
Sorting:
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆130Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆133Updated 3 weeks ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆103Updated 4 years ago
- SystemVerilog Tutorial☆153Updated last month
- A verilog based 5-stage pipelined RISC-V Processor code.☆25Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- Verilog/SystemVerilog Guide☆68Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆49Updated last year
- ☆22Updated 2 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆85Updated 10 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆63Updated last year
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆107Updated 3 weeks ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated last year
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆68Updated 2 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 7 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆45Updated 3 years ago
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆41Updated 2 months ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆42Updated 4 years ago
- opensource EDA tool flor VLSI design☆33Updated last year
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆159Updated 3 weeks ago
- This repo provide an index of VLSI content creators and their materials☆150Updated 10 months ago
- Introductory course into static timing analysis (STA).☆95Updated 2 months ago
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆39Updated last year
- Verilog Fundamentals Explained for Beginners and Professionals☆21Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆96Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆167Updated 7 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆256Updated 3 weeks ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆101Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆25Updated 6 years ago