Alternatives and similar repositories for UVMCourse

Users that are interested in UVMCourse are comparing it to the libraries listed below

• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆41Updated 6 months ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆26Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆37Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆41Updated 4 months ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆74Updated 5 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆66Updated last year
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆52Updated 6 years ago
• mbits-mirafra / axi4_avip
  ☆40Updated 7 months ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆73Updated last year
• shubhi704 / APB-Protocol
  ☆53Updated 4 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆31Updated 11 months ago
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆20Updated 7 months ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆38Updated 9 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆36Updated 10 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆77Updated 5 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆44Updated last year
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆25Updated last year
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆38Updated 5 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆57Updated 8 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆57Updated 6 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆131Updated 10 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆54Updated 4 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆36Updated 8 months ago