A Single Cycle Risc-V 32 bit CPU
☆78Jan 14, 2026Updated 9 months ago
Alternatives and similar repositories for risc-v-single-cycle
Users that are interested in risc-v-single-cycle are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Single Cycle CPU using the RV32I Base Instruction set☆25Nov 5, 2025Updated 11 months ago
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆47Dec 5, 2019Updated 6 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆78May 8, 2021Updated 5 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆45Oct 29, 2023Updated 3 years ago
- Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA☆32Apr 23, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆14Feb 1, 2025Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆90Dec 14, 2023Updated 2 years ago
- Router 1x3 design and uvm verification testbach and coverage report☆14Nov 8, 2024Updated last year
- APB master and slave developed in RTL.☆32Oct 25, 2025Updated last year
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- A progressive course in digital design and verification covering UART, SPI, and I²C — from specification and RTL through UVM-based verifi…☆20May 30, 2026Updated 5 months ago
- My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …☆49Oct 12, 2026Updated 2 weeks ago
- Examples for compiling code using the RISC-V gnu toolchain☆21Jan 3, 2026Updated 9 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- This is a detailed SystemVerilog course☆172Mar 4, 2025Updated last year
- Single Cycle 32 bit MIPS☆20Dec 24, 2022Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆139Dec 17, 2023Updated 2 years ago
- Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.☆161Aug 21, 2026Updated 2 months ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆34Aug 28, 2024Updated 2 years ago
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆33Nov 18, 2025Updated 11 months ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- 32 bit RISC-V CPU implementation in Verilog☆36Feb 9, 2022Updated 4 years ago
- MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…☆25Feb 22, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆15Feb 17, 2023Updated 3 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- Basic RISC-V Test SoC☆212Apr 7, 2019Updated 7 years ago
- A simple 16bit system-on-chip (SoC) consisting of a CPU and GPU☆35Jun 3, 2025Updated last year
- Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.☆31Updated this week
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆29Mar 3, 2026Updated 7 months ago
- DMA Hardware Description with Verilog☆20Dec 20, 2019Updated 6 years ago
- Implementation of RISC-V RV32I☆36Aug 30, 2022Updated 4 years ago
- The VE-HEP RTL and Firmware☆12Mar 19, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repository contains the design files of RISC-V Pipeline Core☆78May 11, 2023Updated 3 years ago
- Parametric AXI4 crossbar in SystemVerilog☆249May 25, 2026Updated 5 months ago
- mWATTBAT: The open source Radar Chip☆12Sep 1, 2025Updated last year
- Advanced Verification Methodologies for RISC-V and related IP☆10Jan 16, 2023Updated 3 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆392Jan 12, 2018Updated 8 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆385Updated this week
- Implementation of a RISC-V CPU in Verilog.☆21Jun 27, 2026Updated 4 months ago