A Single Cycle Risc-V 32 bit CPU
☆73Jan 14, 2026Updated 5 months ago
Alternatives and similar repositories for risc-v-single-cycle
Users that are interested in risc-v-single-cycle are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Feb 1, 2025Updated last year
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆67May 8, 2021Updated 5 years ago
- Single Cycle 32 bit MIPS☆20Dec 24, 2022Updated 3 years ago
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆31Nov 18, 2025Updated 7 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repository contains the design files of RISC-V Single Cycle Core☆85Dec 14, 2023Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆29Aug 28, 2024Updated last year
- Single-Cycle RISC-V Processor in systemverylog☆26Apr 23, 2019Updated 7 years ago
- Implementation of RISC-V RV32I☆30Aug 30, 2022Updated 3 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆27Mar 3, 2026Updated 3 months ago
- DMA Hardware Description with Verilog☆20Dec 20, 2019Updated 6 years ago
- Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA☆30Apr 23, 2023Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 7 years ago
- ☆24Apr 17, 2026Updated 2 months ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- APB master and slave developed in RTL.☆25Oct 25, 2025Updated 8 months ago
- This is a detailed SystemVerilog course☆161Mar 4, 2025Updated last year
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆15Apr 11, 2023Updated 3 years ago
- This repository contains examples of bare metal source code for ADC as described in TB3209 document from Microchip. The code examples wer…☆15Mar 10, 2021Updated 5 years ago
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,559Nov 18, 2025Updated 7 months ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- Logarithmic DAC for AY8913 and SN76489 programmable sound generators (Done as part of Zero To ASIC Analog course)☆11Jun 1, 2024Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆114Jul 2, 2023Updated 2 years ago
- This repository contains the design files of RISC-V Pipeline Core☆73May 11, 2023Updated 3 years ago
- Board definition files and initial example programs☆21Aug 7, 2021Updated 4 years ago
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆60Jan 28, 2025Updated last year
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆46Jul 11, 2025Updated 11 months ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- A tiny RISC-V instruction decoder and instruction set simulator☆36Oct 24, 2025Updated 8 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- ☆10Nov 30, 2022Updated 3 years ago
- My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …☆46Jun 2, 2023Updated 3 years ago
- A fitness app that has on AI camera food detection and calorie info, follow along workout. Built with React Native, Redux Tolkit, Node.js…☆14Feb 3, 2025Updated last year
- Structured UVM Course☆73Jan 4, 2024Updated 2 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆15Feb 17, 2023Updated 3 years ago