Alternatives and similar repositories for risc-v-single-cycle

Users that are interested in risc-v-single-cycle are comparing it to the libraries listed below

• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆120Updated last year
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆43Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆42Updated 6 years ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆18Updated 2 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆57Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆122Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆93Updated 4 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆102Updated 9 months ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆84Updated 6 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆91Updated 2 weeks ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• raysalemi / Python4RTLVerification
  ☆155Updated 2 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆9Updated 8 months ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆24Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆148Updated this week
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆59Updated last year
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆122Updated 4 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆88Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆30Updated 5 years ago
• shubhi704 / APB-Protocol
  ☆42Updated 3 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆142Updated this week
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆76Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆46Updated 10 months ago
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆100Updated 2 months ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆103Updated 4 months ago
• accellera-official / uvm-core
  ☆84Updated 8 months ago